1. 10 Apr, 2019 1 commit
  2. 04 Apr, 2019 1 commit
  3. 03 Apr, 2019 2 commits
  4. 27 Mar, 2019 1 commit
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  6. 19 Mar, 2019 1 commit
  7. 13 Mar, 2019 1 commit
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  10. 04 Mar, 2019 1 commit
  11. 01 Mar, 2019 1 commit
  12. 28 Feb, 2019 1 commit
    • Add and update tests in simple and misc groups · 1eff43de
      Add tests for splitnets command
      Expand coverage for trace command
      Expand coverage for splice command (tests for options)
      Expand coverage for scc command (different loops)
      Expand coverage for rename command
      Change test for passes/techmap/deminout
      Update test for 'dff2dffe -direct' command
      Add test for 'dffsr2dff' command
      Expand coverage for iopadmap command
      SergeyDegtyar committed
  13. 27 Feb, 2019 1 commit
  14. 21 Feb, 2019 1 commit
  15. 20 Feb, 2019 1 commit
    • Add new tests to 'simple' and 'misc' test groups · 50fc2cde
      simple & misc
      ===========
      Note that some of commands you can not test with checking with testbench
      so those place in misc.
      
      1. passes/cmds/add.cc
      Note that here you need to load some existing verilog and add additional
      wires, inputs or outputs
      2. passes/cmds/blackbox.cc
      you could create design with sub module, execute blackbox  and check if
      sub module is replaced with blackbox module.
      3. passes/cmds/bugpoint.cc
      
      4. passes/cmds/chformal.cc
      
      5. passes/cmds/chtype.cc
      
      6. passes/cmds/connect.cc
      Maybe can be covered together with add command
      
      7.passes/cmds/connwrappers.cc
      
      8. passes/cmds/design.cc
      missing covering -import option
      
      9.passes/cmds/plugin.cc
      
      10. passes/cmds/rename.cc
      rename parts of existing design
      
      11. /passes/cmds/select.cc
      Lot of options is not used , so room to improve
      
      12.passes/cmds/setattr.cc
      note there are 3 commands to cover here
      
      13. passes/cmds/setundef.cc
      setting with one, anyseq, anyconst ...
      
      14. passes/sat/assertpmux.cc
      15. passes/sat/async2sync.cc
      16. passes/sat/eval.cc
      17. passes/sat/freduce.cc
      18. passes/sat/miter.cc
      run with -assert option
      19. passes/sat/sat.cc
      many options are not tested
      20. passes/sat/sim.cc
      
      21. passes/techmap/flowmap.cc
      SergeyDegtyar committed
  16. 06 Feb, 2019 1 commit
    • Add test group for equiv_* commands · 5b39f7c6
      Testing problems:
      
      1. coverage_html/passes/equiv/equiv_make.cc.gcov.html - 164-227 are not
      covered;
      2. coverage_html/passes/equiv/equiv_add.cc.gcov.html - is not covered
      ("ERROR: This command must be executed in module context!")
      SergeyDegtyar committed
  17. 05 Feb, 2019 1 commit
    • Add new tests to 'simple' and 'misc' groups. · a92a1d27
      backends
      =======
      1. backends/firrtl/firrtl.cc – skipped because of error:
       ERROR: Unclocked write port 0 on memory top.ram.
      Add model with memory block too, so you can cover line block starting at
      line 419
      
      simple
      =========
      + 1. passes/techmap/attrmap.cc
      There is example in help block create example with
      (* keep="true" *) attribute and run example
      
      + 2. passes/techmap/dff2dffe.cc
      execute with  -unmap parameter
      
      + 3. passes/techmap/dff2dffs.cc
      
      + 4. passes/techmap/extract.cc
      Lot of variations of input parameters is not excersised
      
      ? 5. passes/techmap/extract_counter.cc
      This is specific to greenpak4 architecture, but idea is to have counter
      in design and call this after synth_greenpak
      
      + 6. passes/techmap/shregmap.cc.
      This also seams to be greenpak4 specific, but extracting shift register
      
      misc
      ========
      1. passes/techmap/insbuf.cc
      
      Testing problems:
      1. backends/firrtl/firrtl.cc – skipped because of error:
       ERROR: Unclocked write port 0 on memory top.ram.
      Add model with memory block too, so you can cover line block starting at
      line 419
      2.dff2dffe -direct - skipped: ERROR: Found error in internal cell
      \dffe.$procdff$47 ($dffe) at
      3.insbuf -buf $_BUF_ in out - skipped: ERROR: Found error in internal
      cell
      SergeyDegtyar committed
  18. 29 Jan, 2019 2 commits
  19. 27 Jan, 2019 1 commit
  20. 25 Jan, 2019 3 commits
  21. 24 Jan, 2019 4 commits
  22. 23 Jan, 2019 1 commit
  23. 15 Jan, 2019 1 commit
  24. 02 Jan, 2019 7 commits
  25. 19 Dec, 2018 1 commit
  26. 16 Dec, 2018 1 commit