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yosys-tests
Commit 92201d14 by SergeyDegtyar
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Add tests for issues 88,89,91,93,95,96,98,99,102 

'a'.
parent 1eff43de
Showing with 478 additions and 0 deletions
regression/Makefile
......@@ -69,4 +69,50 @@ $(eval $(call template,issue_00085,issue_00085))
#issue_00086
$(eval $(call template,issue_00086,issue_00086))
#issue_00088
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top.v' to AST representation.
#top.v:6: ERROR: syntax error, unexpected $undefined
#$(eval $(call template,issue_00089,issue_00089))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
# correct behavior
#../top.v:1: syntax error
#../top.v:1: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00093,issue_00093))
#issue_00095
#../top.v:1: syntax error
#../top.v:1: error: Invalid variable list in port declaration.
#../top.v:1: error: duplicate declaration for net or variable 'c' in 'a'.
#$(eval $(call template,issue_00095,issue_00095))
#issue_00096
#../top.v:2: syntax error
#../top.v:1: error: syntax error in integer variable list.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00096,issue_00096))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
#issue_00099
$(eval $(call template,issue_00099,issue_00099))
#issue_00102
$(eval $(call template,issue_00102,issue_00102))
#issue_00111
$(eval $(call template,issue_00111,issue_00111))
.PHONY: all clean
regression/issue_00088/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00088/top.v 0 → 100644
parameter X = 2;
module top(b);
input b;
parameter Y = 3;
endmodule
regression/issue_00089/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00089/top.v 0 → 100644
module top(A, clk, rst);
input clk, rst;
output A;
always @(posedge clk, posedge rst) begin
A <= '0';
end; // << like this
endmodule
regression/issue_00091/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00091/top.v 0 → 100644
module top(A, clk, rst);
input clk, rst;
output A;
parameter GPIO_COUNT = 16;
initial begin
if (GPIO_COUNT < 0 || GPIO_COUNT > 16) begin
$display("Parameter Error: GPIO_COUNT must be in range 0..16");
$finish;
end
end
endmodule
regression/issue_00093/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00093/top.v 0 → 100644
module top(b);inout b;reg c;assign+0-c=b;endmodule
regression/issue_00095/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00095/top.v 0 → 100644
module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule
regression/issue_00096/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00096/top.v 0 → 100644
module top(b);integer
inout b;reg c;assign&0=0;assign 0=0;always
i=0;always
if(8)b=_;always
if(8)b=M&0;endmodule
regression/issue_00098/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
always @(clk)
a <= a + 1;
top uut (
.a (a),
.z (z)
);
assert_Z check_output(clk,z[0]);
endmodule
regression/issue_00098/top.v 0 → 100644
module top(a,z);
input [7:0] a;
output [7:0] z;
parameter pos = 1;
assign z = ff(a);
function [7:0] ff;
parameter pos2 = pos + 1;
input [7:0] arg1;
begin
ff = arg1[pos2:0];
end
endfunction
endmodule
regression/issue_00099/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
wire o1,o2,o3;
always @(clk)
a <= a + 1;
top uut (
.in (a),
.out (z),
.out1 (o1),
.out2 (o2),
.out3 (o3)
);
assert_Z check_output1(clk,o1);
assert_Z check_output2(clk,o2);
assert_Z check_output3(clk,o3);
endmodule
regression/issue_00099/top.v 0 → 100644
module top(in, out, out1, out2, out3);
input [7:0] in;
output [7:0] out;
output out1;
output out2;
output out3;
parameter p = 23;
function [7:0] test1;
input [7:0] i;
parameter p = 42;
begin
test1 = i + p;
end
endfunction
function [7:0] test2;
input [7:0] i;
parameter p2 = p+42;
begin
test2 = i + p2;
end
endfunction
function [7:0] test3;
input [7:0] i;
begin
test3 = i + p;
end
endfunction
assign out1 = test1(in);
assign out2 = test2(in);
assign out3 = test3(in);
endmodule
regression/issue_00102/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [35:0] b;
top uut (
.a (clk),
.b (b)
);
assert_Z check_output1(clk,b[0]);
endmodule
regression/issue_00102/top.v 0 → 100644
module top (
a, b
);
input a;
output [35:0] b;
reg [35:0] G;
reg F;
reg H;
reg I;
reg J;
reg [5:0] K;
reg [9:0] L;
reg [9:0] M;
assign b = muxer(G, {L , H , F , M, J , I}, K, 24, 0);
function [35:0] muxer;
input [35:0] vector;
input [23:0] slice;
input [5:0] index;
input size;
integer size;
input offset;
integer offset;
integer i;
reg [35:0] muxed_value;
begin
muxed_value = vector;
for (i = 0; i < 24; i = i+1)
muxed_value[index * size + offset + i] = slice[i];
muxer = muxed_value;
end
endfunction
endmodule
regression/issue_00111/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [127:0] state,key = 0;
wire [127:0] out;
/*always @(posedge clk)
begin
state = state + 2300;
key = key + 2500;
end
top uut (
.state (state ),
.key (key ),
.out (out )
);*/
/*genvar index;
generate
for (index=0; index < 128; index=index+25)
begin: gen_code_label
assert_Z check_output(clk,out[index]);
end
endgenerate*/
assert_Z check_output(clk,out[0]);
endmodule
regression/scripts/issue_00088.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00089.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00091.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00093.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00095.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00096.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00098.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00099.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00102.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00111.ys 0 → 100644
read_verilog ../top.v
synth -top top
splitnets -ports
hierarchy -check
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
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