Commit e0c895b0 by SergeyDegtyar

add tests for synth_anlogic and 'regression'

1. Add tests for synth_anlogic command
Now this tests are commented because of:
+ iverilog -o testbench ../testbench.v synth.v ../../common.v
../../../../../techlibs/common/simcells.v
../../../../../techlibs/anlogic/cells_sim.v
../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to bind
wire/reg/memory `A' in `testbench.uut._09_'
../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to
elaborate r-value: (INIT)>>(A)
2 error(s) during elaboration.

2. Add 'regression' test
parent eb937aff
......@@ -20,6 +20,12 @@ endef
#achronix (in the code '-flatten' but in the help '-noflatten')
$(eval $(call template,synth_achronix,synth_achronix synth_achronix_top synth_achronix_vout synth_achronix_run synth_achronix_noflatten synth_achronix_retime))
#anlogic
#../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to bind wire/reg/memory `A' in `testbench.uut._09_'
#../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to elaborate r-value: (INIT)>>(A)
#$(eval $(call template,synth_anlogic,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
#$(eval $(call template,synth_anlogic_fulladder,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
#coolrunner2
$(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
......
......@@ -13,6 +13,8 @@ if [ "$1" = "synth_ecp5" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
elif [ "$1" = "synth_achronix" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/achronix/speedster22i/cells_sim.v
elif [ "$1" = "synth_anlogic" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
elif [ "$1" = "synth_coolrunner2" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
elif [ "$1" = "synth_gowin" ]; then
......
read_verilog ../top.v
synth_anlogic
write_verilog synth.v
read_verilog ../top.v
synth_anlogic -edif edif.edif
write_verilog synth.v
read_verilog ../top.v
synth_anlogic -json json.json
write_verilog synth.v
read_verilog ../top.v
synth_anlogic -noflatten
write_verilog synth.v
read_verilog ../top.v
synth_anlogic -retime
write_verilog synth.v
read_verilog ../top.v
synth_anlogic -run begin:json
write_verilog synth.v
read_verilog ../top.v
synth_anlogic -top top
write_verilog synth.v
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
/alu/work_*/
/.stamp
all: work
touch .stamp
clean::
rm -f .stamp
define template
$(foreach design,$(1),
$(foreach script,verify falsify $(2),
work:: $(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp:
bash run.sh $(design) $(script)
clean::
rm -rf $(design)/work_$(script)
))
endef
#case_stmt_assertion
$(eval $(call template,case_stmt_assertion,case_stmt_assertion))
.PHONY: all clean
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [3:0] D;
reg [1:0] S = 0;
reg [3:0] control = 0;
always @(posedge clk)
case(S)
2'b00: begin end
2'b01: control <= 4'h2;
2'b10: control <= 4'h4;
2'b11: control <= 4'h8;
default: control <= 4'h0;
endcase
top uut (
.clk (clk ),
.I (S ),
.O (D )
);
always @(posedge clk) begin
//#3;
S <= S + 1;
end
check_output out_test( .A(control), .B(D));
endmodule
module check_output(input [3:0] A, input [3:0] B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module mcve(i_clk, i_value, o_value);
input wire i_clk;
input wire [1:0] i_value;
output reg [3:0] o_value;
initial o_value = 0;
always @(posedge i_clk)
case(i_value)
2'b00: begin end
`ifndef BUG
2'b01: o_value <= 4'h2;
`else
2'b01: o_value <= 4'h3;
`endif
2'b10: o_value <= 4'h4;
2'b11: o_value <= 4'h8;
default: o_value <= 4'h1;
endcase
endmodule
module top (
input clk,
input [1:0] I,
output [3:0] O
);
mcve u_mcve (
.i_clk(clk),
.i_value(I),
.o_value(O)
);
endmodule
module mcve(i_clk, i_value, o_value);
input wire i_clk;
input wire [1:0] i_value;
output reg [3:0] o_value;
initial o_value = 0;
always @(posedge i_clk)
case(i_value)
2'b00: begin end
`ifndef BUG
2'b01: o_value <= 4'h2;
`else
2'b01: o_value <= 4'h3;
`endif
2'b10: o_value <= 4'h4;
2'b11: o_value <= 4'h8;
default: o_value <= 4'h1;
endcase
always @(*)
case(o_value)
4'h0: begin end
4'h1: assert(o_value == 4'h1);
`ifndef BUG
4'h2: assert(o_value == 4'h2);
`else
4'h2: assert(o_value == 4'h3);
`endif
4'h4: assert(o_value == 4'h4);
4'h8: assert(o_value == 4'h8);
default: assert(0);
endcase
endmodule
module top (
input clk,
input [1:0] I,
output [3:0] O
);
mcve u_mcve (
.i_clk(clk),
.i_value(I),
.o_value(O)
);
endmodule
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
#!/bin/bash
set -ex
test -d $1
if [ "$2" != "verify" -a "$2" != "falsify" ]; then
test -f scripts/$2.ys
fi
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
if [ "$2" = "verify" ]; then
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v
elif [ "$2" = "falsify" ]; then
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v
else
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v)
fi
if [ "$2" = "falsify" ]; then
if vvp -N testbench > testbench.log 2>&1; then
echo FAIL > ${1}_${2}.status
elif ! grep 'ERROR' testbench.log || grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
else
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
fi
touch .stamp
read -formal ../top_assert.v
prep -top mcve
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment