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yosys-tests
Commit 397f3405 by SergeyDegtyar
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Add new tests to 'regression' test group 

testing problems:
Issue #61 does not contain enough info.
Issues #82 and #83 I skipped because of errors.

---------------------

All of tasks will go to group regression, please change naming
convention there so files are named according to issue number (for
example issue_86 for directory and issue_86.ys script)
directory should contain exact example from issue, or in case it was
just generally described you can create your own example according to
explanation.

Idea for these tasks is not getting greater coverage  but making sure
old issues fixed are never broken again. Usually problem was failing of
yosys to generate any kind of output, in most of cases bellow, so just
checking if yosys did not assert any error is enough at least for these.
Issues bellow are taken from last two pages on issue tracker. Some of
these can really be trivial, and issue contains all info you need. Some
maybe need more thinking to be sure that you understood issue correctly.
In any case you are free to continue going trough the list of issues and
select new from it to cover.
I will see to crate some online spreadsheet that will have issue number,
type (if it is something that needed to be fixed or was a new feature or
some user error, and will have a status if it is covered by test or not.
That way we can have better overview what is going on.
So if you see that something is without a way to reproduce, or it was
user error just skip it, and when we have a spreadsheet we can update
there.

1. https://github.com/YosysHQ/yosys/issues/86
2. https://github.com/YosysHQ/yosys/issues/85
3. https://github.com/YosysHQ/yosys/issues/84
4. https://github.com/YosysHQ/yosys/issues/83
5. https://github.com/YosysHQ/yosys/issues/82
6. https://github.com/YosysHQ/yosys/issues/81
7. https://github.com/YosysHQ/yosys/issues/78
8. https://github.com/YosysHQ/yosys/issues/71
9. https://github.com/YosysHQ/yosys/issues/67
10. https://github.com/YosysHQ/yosys/issues/65
11. https://github.com/YosysHQ/yosys/issues/61
12. https://github.com/YosysHQ/yosys/issues/59
13. https://github.com/YosysHQ/yosys/issues/41
14. https://github.com/YosysHQ/yosys/issues/18
parent caadcd1c
Showing with 655 additions and 3 deletions
regression/Makefile
......@@ -20,4 +20,53 @@ endef
#case_stmt_assertion
$(eval $(call template,case_stmt_assertion,case_stmt_assertion))
#issue_00018
$(eval $(call template,issue_00018,issue_00018))
#issue_00041
$(eval $(call template,issue_00041,issue_00041))
#issue_00059
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
$(eval $(call template,issue_00065,issue_00065))
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
#issue_00071
$(eval $(call template,issue_00071,issue_00071))
#issue_00078 What should be in top.v?
$(eval $(call template,issue_00078,issue_00078))
#issue_00081
$(eval $(call template,issue_00081,issue_00081))
#issue_00082
#yosys> read_verilog top_fault.v
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top_fault.v' to AST representation.
#top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
#
#$(eval $(call template,issue_00082,issue_00082))
#issue_00083
#Warning: Deep recursion in AST simplifier.
#Does this design contain insanely long expressions?
#run.sh: line 21: 17264 Segmentation fault (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
#make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
#
#$(eval $(call template,issue_00083,issue_00083))
#issue_00084
$(eval $(call template,issue_00084,issue_00084))
#issue_00085
$(eval $(call template,issue_00085,issue_00085))
#issue_00086
$(eval $(call template,issue_00086,issue_00086))
.PHONY: all clean
regression/issue_00018/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00018/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
regression/issue_00041/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00041/top.v 0 → 100644
module top(b);
input b;
task DoSomething(input [7:0] A);
endtask
endmodule
regression/issue_00059/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00059/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00065/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00065/top.v 0 → 100644
module top(
alu_data_d_in,
alu_data_d_out
);
input [7:0]alu_data_d_in;
output[7:0]alu_data_d_out;
wire [7:0]swap_out;
genvar i;
generate
for ( i = 7 ; ( i >= 4 ) ; i = ( i - 1 ) )
begin : swap_h
assign swap_out[i] = alu_data_d_in[( ( i - 4 ) )];
end
endgenerate
generate
//for ( i = 0 ; ( i <4 ) ; i = ( i + 1 ) ) //OK
for ( i = 3 ; ( i >=0 ) ; i = ( i - 1 ) ) //FAIL
begin : swap_l
assign swap_out[i] = alu_data_d_in[(i+4 )];
end
endgenerate
assign alu_data_d_out = swap_out;
endmodule
regression/issue_00067/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00067/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00067/top_fault.v 0 → 100644
module top(input en, output reg y);
always @*
y = en & !y;
endmodule
regression/issue_00071/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00071/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00071/top_fault.v 0 → 100644
module top(b);
input b;
reg [31:0] reg_32 = 32'bX;
endmodule
regression/issue_00078/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00078/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00078/top_fault.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00081/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00081/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00081/top_fault.v 0 → 100644
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
endmodule
module demo_002(y0, y1, y2, y3);
output [63:0] y0, y1, y2, y3;
assign y0 = 1'b_ >= (-1 * -1.17);
assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
assign y3 = 1 ? -1 : 'd0;
endmodule
regression/issue_00082/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00082/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00082/top_fault.v 0 → 100644
module a(b);
input b;
reg c;
task a(b);
endmodule
regression/issue_00083/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00083/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00083/top_fault.v 0 → 100644
module a(b);
input b;
reg c;parameter
signed b=b;
endmodule
regression/issue_00084/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [9:0] addr = 0;
reg ce = 0;
wire [7:0] q;
top uut (
.clk(clk),
.addr(addr),
.ce(ce),
.q(q)
);
always @(posedge clk) begin
addr <= addr + 1;
end
always @(posedge clk) begin
#3;
ce <= !ce;
end
uut_mem_checker q_test(.clk(clk), .en(ce), .A(q));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'b00000000)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00084/top.v 0 → 100644
module top (addr, ce, q, clk);
input clk;
input [9:0] addr;
input ce;
output reg [7:0] q;
reg [7:0] ram[1023:0];
always @(posedge clk)
begin
if (ce)
begin
q <= ram[addr];
end
end
endmodule
regression/issue_00085/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00085/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00085/top_fault.v 0 → 100644
module a;assign a = 0'sh0;
endmodule
regression/issue_00086/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00086/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00086/top_fault.v 0 → 100644
module top(b);
input b;
reg N=0.0/0'H0;
endmodule
regression/run.sh
......@@ -12,12 +12,12 @@ mkdir $1/work_$2
cd $1/work_$2
if [ "$2" = "verify" ]; then
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
elif [ "$2" = "falsify" ]; then
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
else
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v)
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v) ../../../../../techlibs/xilinx/brams_bb.v
fi
if [ "$2" = "falsify" ]; then
......
regression/scripts/issue_00018.ys 0 → 100644
read_verilog ../top.v
synth -top top
select -assert-any w:*i
write_verilog synth.v
regression/scripts/issue_00041.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00059.ys 0 → 100644
read_verilog ../top.v
#Myname: added some comment with a colon
synth -top top
write_verilog synth.v
regression/scripts/issue_00065.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00067.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00071.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00078.ys 0 → 100644
read_verilog ../top.v
hierarchy
splitnets -ports
write_verilog synth.v
regression/scripts/issue_00081.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00082.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00083.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00084.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -top top
write_verilog synth.v
regression/scripts/issue_00085.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00086.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
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