Merge branch 'master' into master

bigsim/.gitignore

 /.stamp
 /*_cmos.status
 /*_ice40.status
+/*_falsify.status
 /*/work_sim
 /*/work_cmos
 /*/work_ice40
+/*/work_falsify
 /*/.stamp_sim
 /*/.stamp_cmos
 /*/.stamp_ice40
+/*/.stamp_falsify

bigsim/Makefile

@@ -5,12 +5,16 @@ clean::
 	rm -f .stamp
 
 define template
-work:: $(addprefix $(1)/.stamp_,sim $(2))
+work:: $(addprefix $(1)/.stamp_,sim falsify $(2))
 
 $(1)/.stamp_sim:
 	bash run.sh $(1) sim
 	touch $$@
 
+$(1)/.stamp_falsify: $(1)/.stamp_sim
+	bash run.sh $(1) falsify
+	touch $$@
+
 $(1)/.stamp_cmos: $(1)/.stamp_sim
 	bash run.sh $(1) cmos
 	touch $$@
@@ -21,6 +25,7 @@ $(1)/.stamp_ice40: $(1)/.stamp_sim
 
 clean::
 	rm -rf $(1)/.stamp_* $(1)/work_*
+	rm -f $(1)_cmos.status $(1)_ice40.status $(1)_falsify.status
 endef
 
 $(eval $(call template,navre,cmos ice40))

bigsim/navre/rtl/softusb_navre.v

@@ -136,7 +136,9 @@ reg [7:0] GPR_Rr;
 always @(*) begin
 	case(Rr)
 		default: GPR_Rr = GPR_Rr8;
+`ifndef BUG
 		5'd24: GPR_Rr = U[7:0];
+`endif
 		5'd25: GPR_Rr = U[15:8];
 		5'd26: GPR_Rr = pX[7:0];
 		5'd27: GPR_Rr = pX[15:8];

bigsim/run.sh

@@ -16,6 +16,9 @@ case "$2" in
 	sim)
 		iverilog_cmd="$iverilog_cmd $rtl_files"
 		;;
+	falsify)
+		iverilog_cmd="$iverilog_cmd -DBUG $rtl_files"
+		;;
 	cmos)
 		yosys -ql synthlog.txt -p "synth -top $TOP; abc -g cmos4; write_verilog synth.v" $rtl_files
 		iverilog_cmd="$iverilog_cmd synth.v"
@@ -36,10 +39,16 @@ $iverilog_cmd
 
 vvp -N sim | pv -l > output.txt
 
-if [ "$2" != "sim" ]; then
+if [ "$2" = "falsify" ]; then
+	if cmp output.txt ../work_sim/output.txt; then
+		echo FAIL > ../../${1}_${2}.status
+	else
+		echo pass > ../../${1}_${2}.status
+	fi
+elif [ "$2" != "sim" ]; then
 	if cmp output.txt ../work_sim/output.txt; then
 		echo pass > ../../${1}_${2}.status
 	else
-		echo fail > ../../${1}_${2}.status
+		echo FAIL > ../../${1}_${2}.status
 	fi
 fi

simple/Makefile

@@ -6,7 +6,7 @@ clean::
 
 define template
 $(foreach design,$(1),
-$(foreach script,$(2),
+$(foreach script,verify falsify $(2),
 work:: $(design)/work_$(script)/.stamp
 
 $(design)/work_$(script)/.stamp:

simple/alu/top.v

@@ -13,7 +13,11 @@ module top (
 		4: dout <= dinA << dinB;
 		5: dout <= dinA & dinB;
 		6: dout <= dinA | dinB;
+`ifndef BUG
 		7: dout <= dinA ^ dinB;
+`else
+		7: dout <= -dinA ^ dinB;
+`endif
 		endcase
 	end
 endmodule

simple/run.sh

@@ -2,22 +2,41 @@
 
 set -ex
 test -d $1
-test -f scripts/$2.ys
+
+if [ "$2" != "verify" -a "$2" != "falsify" ]; then
+	test -f scripts/$2.ys
+fi
 
 rm -rf $1/work_$2
 mkdir $1/work_$2
 cd $1/work_$2
 
-yosys -ql yosys.log ../../scripts/$2.ys
-iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
+if [ "$2" = "verify" ]; then
+	iverilog -o testbench ../testbench.v ../../common.v ../top.v
+elif [ "$2" = "falsify" ]; then
+	iverilog -DBUG -o testbench ../testbench.v ../../common.v ../top.v
+else
+	yosys -ql yosys.log ../../scripts/$2.ys
+	iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/common/simcells.v)
+fi
 
-if ! vvp -N testbench > testbench.log 2>&1; then
-	grep 'ERROR' testbench.log
-	echo fail > ${1}_${2}.status
-elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo fail > ${1}_${2}.status
+if [ "$2" = "falsify" ]; then
+	if vvp -N testbench > testbench.log 2>&1; then
+		echo FAIL > ${1}_${2}.status
+	elif ! grep 'ERROR' testbench.log || grep 'OKAY' testbench.log; then
+		echo FAIL > ${1}_${2}.status
+	else
+		echo pass > ${1}_${2}.status
+	fi
 else
-	echo pass > ${1}_${2}.status
+	if ! vvp -N testbench > testbench.log 2>&1; then
+		grep 'ERROR' testbench.log
+		echo FAIL > ${1}_${2}.status
+	elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+		echo FAIL > ${1}_${2}.status
+	else
+		echo pass > ${1}_${2}.status
+	fi
 fi
 
 touch .stamp