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yosys-tests
Commit 461b4673 by SergeyDegtyar
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Add tests for issues 111 - 195

parent 92201d14
Showing with 1074 additions and 44 deletions
regression/Makefile
......@@ -6,7 +6,7 @@ clean::
define template
$(foreach design,$(1),
$(foreach script,verify falsify $(2),
$(foreach script,$(2),
work:: $(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp:
......@@ -38,7 +38,7 @@ $(eval $(call template,issue_00067,issue_00067))
#issue_00071
$(eval $(call template,issue_00071,issue_00071))
#issue_00078 What should be in top.v?
#issue_00078
$(eval $(call template,issue_00078,issue_00078))
#issue_00081
......@@ -73,34 +73,19 @@ $(eval $(call template,issue_00086,issue_00086))
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top.v' to AST representation.
#top.v:6: ERROR: syntax error, unexpected $undefined
#$(eval $(call template,issue_00089,issue_00089))
$(eval $(call template,issue_00089,issue_00089))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
# correct behavior
#../top.v:1: syntax error
#../top.v:1: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00093,issue_00093))
$(eval $(call template,issue_00093,issue_00093))
#issue_00095
#../top.v:1: syntax error
#../top.v:1: error: Invalid variable list in port declaration.
#../top.v:1: error: duplicate declaration for net or variable 'c' in 'a'.
#$(eval $(call template,issue_00095,issue_00095))
$(eval $(call template,issue_00095,issue_00095))
#issue_00096
#../top.v:2: syntax error
#../top.v:1: error: syntax error in integer variable list.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00096,issue_00096))
$(eval $(call template,issue_00096,issue_00096))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
......@@ -114,5 +99,53 @@ $(eval $(call template,issue_00102,issue_00102))
#issue_00111
$(eval $(call template,issue_00111,issue_00111))
#issue_00114
$(eval $(call template,issue_00114,issue_00114))
#issue_00126
$(eval $(call template,issue_00126,issue_00126))
#issue_00128
$(eval $(call template,issue_00128,issue_00128))
#issue_00132
$(eval $(call template,issue_00132,issue_00132))
#issue_00133
$(eval $(call template,issue_00133,issue_00133))
#issue_00134
$(eval $(call template,issue_00134,issue_00134))
#issue_00160
$(eval $(call template,issue_00160,issue_00160))
#issue_00171
$(eval $(call template,issue_00171,issue_00171))
#issue_00173
$(eval $(call template,issue_00173,issue_00173))
#issue_00174
$(eval $(call template,issue_00174,issue_00174))
#issue_00175
$(eval $(call template,issue_00175,issue_00175))
#issue_00182
$(eval $(call template,issue_00182,issue_00182))
#issue_00183
$(eval $(call template,issue_00183,issue_00183))
#issue_00186
$(eval $(call template,issue_00186,issue_00186))
#issue_00194
$(eval $(call template,issue_00194,issue_00194))
#issue_00195
$(eval $(call template,issue_00195,issue_00195))
.PHONY: all clean
regression/common.v
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#2
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
......@@ -33,6 +34,18 @@ module assert_Z(input clk, input A);
end
endmodule
module assert_X(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
......
regression/issue_00111/testbench.v
......@@ -21,13 +21,13 @@ module testbench;
begin
state = state + 2300;
key = key + 2500;
end
end*/
top uut (
.state (state ),
.key (key ),
.out (out )
);*/
);
/*genvar index;
generate
......
regression/issue_00114/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.clock (clk )
);
endmodule
regression/issue_00114/top.v 0 → 100644
module top(
input wire clock
);
localparam COUNT = 1600;
reg buffer[0:COUNT-1];
always @(posedge clock) begin : GENERATE
integer ii;
for(ii = 0; ii < COUNT; ii = ii + 1) begin
buffer[ii] <= 1'b0;
end
end
endmodule
regression/issue_00126/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
always @(posedge clk)
in = in + 1;
top uut (
.in_a(in),
.out_vt(out)
);
endmodule
regression/issue_00126/top.v 0 → 100644
module top (in_a, out_vt);
input [1:0] in_a;
output out_vt;
reg [2:0] result;
assign out_vt = result;
always @(*)
begin
result = 3'b000;
case (in_a)
2'b00 : begin
result = 3'b101;
end
2'b01: begin
result = 3'b001;
end
default;
endcase
end
endmodule
regression/issue_00128/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00128/top.v 0 → 100644
module top(b);
input b;
initial $display("%m");
endmodule
regression/issue_00132/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00132/top.v 0 → 100644
module submod(input [7:0] a, output [7:0] y);
parameter integer increment = 0;
initial begin
if (increment == 0) begin
$display("increment parameter must have a non-zero value!");
//$stop;
end
end
assign y = a + increment;
endmodule
module top(input [7:0] a, output [7:0] y);
parameter integer incr = 0;
submod #(incr) submod_instance (a, y);
endmodule
regression/issue_00133/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00133/top.v 0 → 100644
module top(input [7:0] a, output reg [7:0] y);
always @* begin:myblock
reg [7:0] myarray [0:1];
myarray[0] = a + 23;
myarray[1] = myarray[0] - 42;
y = myarray[1] + 19;
end
endmodule
regression/issue_00134/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] a = 0;
wire [15:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.in_data (a ),
.do (y )
);
genvar index;
generate
for (index=0; index <= 15; index=index+1)
begin: gen_code_label
assert_X check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00134/top.v 0 → 100644
module top ( in_data, do );
input [15:0] in_data;
output [15:0] do;
wire [15:0] out_data;
assign do = out_data;
always @ (*)
begin
Test_task(in_data, out_data);
// out_data = in_data; // This works but above task doesn't
end
task Test_task;
input [15:0] in_d;
output [15:0] out_data;
begin
out_data = in_d;
end
endtask
endmodule
regression/issue_00160/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg ce = 1;
wire d;
always @(posedge clk)
begin
a = a + 1;
end
top uut (
.CLKIN(clk),
.A (a ),
.CE (ce),
.D1 (d)
);
assert_X check_output(clk,d);
endmodule
regression/issue_00160/top.v 0 → 100644
module Add2 (input [1:0] I0, input [1:0] I1, output [1:0] O);
wire inst0_O;
wire inst1_CO;
wire inst2_O;
wire inst3_CO;
SB_LUT4 #(.LUT_INIT(16'hC33C)) inst0 (.I0(1'b0), .I1(I0[0]), .I2(I1[0]), .I3(1'b0), .O(inst0_O));
SB_CARRY inst1 (.I0(I0[0]), .I1(I1[0]), .CI(1'b0), .CO(inst1_CO));
SB_LUT4 #(.LUT_INIT(16'hC33C)) inst2 (.I0(1'b0), .I1(I0[1]), .I2(I1[1]), .I3(inst1_CO), .O(inst2_O));
SB_CARRY inst3 (.I0(I0[1]), .I1(I1[1]), .CI(inst1_CO), .CO(inst3_CO));
assign O = {inst2_O,inst0_O};
endmodule
module Register2CE (input [1:0] I, output [1:0] O, input CLK, input CE);
wire inst0_Q;
wire inst1_Q;
//SB_DFFE #(.INIT(1'b0)) inst0 (.C(CLK), .E(CE), .D(I[0]), .Q(inst0_Q));
//SB_DFFE #(.INIT(1'b0)) inst1 (.C(CLK), .E(CE), .D(I[1]), .Q(inst1_Q));
SB_DFFE inst0 (.C(CLK), .E(CE), .D(I[0]), .Q(inst0_Q));
SB_DFFE inst1 (.C(CLK), .E(CE), .D(I[1]), .Q(inst1_Q));
assign O = {inst1_Q,inst0_Q};
endmodule
module top (input CLKIN, input A, input CE, output D1);
wire [1:0] inst0_O;
wire [1:0] inst1_O;
Add2 inst0 (.I0(inst1_O), .I1({1'b0,1'b1}), .O(inst0_O));
Register2CE inst1 (.I(inst0_O), .O(inst1_O), .CLK(CLKIN), .CE(CE));
assign D1 = inst1_O[1];
endmodule
regression/issue_00171/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 1;
reg ce = 1;
wire [3:0] count;
reg [3:0] count_p;
always @(posedge clk)
begin
rst = 0;
end
always @(posedge clk)
if (rst)
count_p <= 4'd0;
else if (ce)
count_p <= count_p + 4'd1;
top uut (
.clk(clk),
.rst (rst ),
.en (ce),
.count (count)
);
genvar index;
generate
for (index=0; index <= 3; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,count[index],count_p[index]);
end
endgenerate
endmodule
regression/issue_00171/top.v 0 → 100644
module top (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
if (rst)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
endmodule
regression/issue_00173/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [2:0] o;
reg [2:0] i;
always @(posedge clk)
i <= i + 1;
top uut (i[0],i[1],i[2],o[0],o[1],o[2]);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],i[index]);
end
endgenerate
endmodule
regression/issue_00173/top.v 0 → 100644
module top
(
input ai, bi, ci,
output reg ao, bo, co
);
always@*
begin
ao=ai;
bo=bi;
co=ci;
{co,co,bo,ao} = {ai,bi,ai,ci}; // Error: multiple assignment to 'co' with blocking assignment
end
endmodule
regression/issue_00174/abc.rc 0 → 100644
# global parameters
set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
set backup # saves backup networks retrived by "undo" and "recall"
set savesteps 1 # sets the maximum number of backup networks to save
set progressbar # display the progress bar
# program names for internal calls
set dotwin dot.exe
set dotunix dot
set gsviewwin gsview32.exe
set gsviewunix gv
set siswin sis.exe
set sisunix sis
set mvsiswin mvsis.exe
set mvsisunix mvsis
set capowin MetaPl-Capo10.1-Win32.exe
set capounix MetaPl-Capo10.1
set gnuplotwin wgnuplot.exe
set gnuplotunix gnuplot
# standard aliases
alias b balance
alias cl cleanup
alias clp collapse
alias esd ext_seq_dcs
alias f fraig
alias fs fraig_sweep
alias fsto fraig_store
alias fres fraig_restore
alias ft fraig_trust
alias lp lutpack
alias pd print_dsd
alias pex print_exdc -d
alias pf print_factor
alias pfan print_fanio
alias pl print_level
alias pio print_io
alias pk print_kmap
alias ps print_stats
alias psu print_supp
alias psy print_symm
alias pun print_unate
alias q quit
alias r read
alias r3 retime -M 3
alias r3f retime -M 3 -f
alias r3b retime -M 3 -b
alias ren renode
alias rh read_hie
alias rl read_blif
alias rb read_bench
alias ret retime
alias rp read_pla
alias rt read_truth
alias rv read_verilog
alias rvl read_verlib
alias rsup read_super mcnc5_old.super
alias rlib read_library
alias rlibc read_library cadence.genlib
alias rw rewrite
alias rwz rewrite -z
alias rf refactor
alias rfz refactor -z
alias re restructure
alias rez restructure -z
alias rs resub
alias rsz resub -z
alias sa set autoexec ps
alias scl scleanup
alias sif if -s
alias so source -x
alias st strash
alias sw sweep
alias ssw ssweep
alias tr0 trace_start
alias tr1 trace_check
alias trt "r c.blif; st; tr0; b; tr1"
alias u undo
alias w write
alias wa write_aiger
alias wb write_bench
alias wc write_cnf
alias wh write_hie
alias wl write_blif
alias wp write_pla
alias wv write_verilog
# standard scripts
alias share "b; ren -s; fx; b"
alias sharedsd "b; ren -b; dsd -g; sw; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias resyn2a "b; rw; b; rw; rwz; b; rwz; b"
alias resyn3 "b; rs; rs -K 6; b; rsz; rsz -K 6; b; rsz -K 5; b"
alias compress "b -l; rw -l; rwz -l; b -l; rwz -l; b -l"
alias compress2 "b -l; rw -l; rf -l; b -l; rw -l; rwz -l; b -l; rfz -l; rwz -l; b -l"
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
alias rwsat "st; rw -l; b -l; rw -l; rf -l"
alias rwsat2 "st; rw -l; b -l; rw -l; rf -l; fraig; rw -l; b -l; rw -l; rf -l"
alias shake "st; ps; sat -C 5000; rw -l; ps; sat -C 5000; b -l; rf -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000; rwz -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000"
# resubstitution scripts for the IWLS paper
alias src_rw "st; rw -l; rwz -l; rwz -l"
alias src_rs "st; rs -K 6 -N 2 -l; rs -K 9 -N 2 -l; rs -K 12 -N 2 -l"
alias src_rws "st; rw -l; rs -K 6 -N 2 -l; rwz -l; rs -K 9 -N 2 -l; rwz -l; rs -K 12 -N 2 -l"
alias resyn2rs "b; rs -K 6; rw; rs -K 6 -N 2; rf; rs -K 8; b; rs -K 8 -N 2; rw; rs -K 10; rwz; rs -K 10 -N 2; b; rs -K 12; rfz; rs -K 12 -N 2; rwz; b"
alias compress2rs "b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; rs -K 8 -N 2 -l; rw -l; rs -K 10 -l; rwz -l; rs -K 10 -N 2 -l; b -l; rs -K 12 -l; rfz -l; rs -K 12 -N 2 -l; rwz -l; b -l"
# experimental implementation of don't-cares
alias resyn2rsdc "b; rs -K 6 -F 2; rw; rs -K 6 -N 2 -F 2; rf; rs -K 8 -F 2; b; rs -K 8 -N 2 -F 2; rw; rs -K 10 -F 2; rwz; rs -K 10 -N 2 -F 2; b; rs -K 12 -F 2; rfz; rs -K 12 -N 2 -F 2; rwz; b"
alias compress2rsdc "b -l; rs -K 6 -F 2 -l; rw -l; rs -K 6 -N 2 -F 2 -l; rf -l; rs -K 8 -F 2 -l; b -l; rs -K 8 -N 2 -F 2 -l; rw -l; rs -K 10 -F 2 -l; rwz -l; rs -K 10 -N 2 -F 2 -l; b -l; rs -K 12 -F 2 -l; rfz -l; rs -K 12 -N 2 -F 2 -l; rwz -l; b -l"
# minimizing for FF literals
alias fflitmin "compress2rs; ren; sop; ps -f"
# temporaries
#alias t "rvl th/lib.v; rvv th/t2.v"
#alias t "so c/pure_sat/test.c"
#alias t "r c/14/csat_998.bench; st; ps"
#alias t0 "r res.blif; aig; mfs"
#alias t "r res2.blif; aig; mfs"
#alias tt "r a/quip_opt/nut_001_opt.blif"
#alias ttb "wh a/quip_opt/nut_001_opt.blif 1.blif"
#alias ttv "wh a/quip_opt/nut_001_opt.blif 1.v"
alias reach "st; ps; compress2; ps; qrel; ps; compress2; ps; qreach -v; ps"
alias qs1 "qvar -I 96 -u; ps; qbf -P 96"
alias qs2 "qvar -I 96 -u; qvar -I 97 -u; ps; qbf -P 96"
alias qs3 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; ps; qbf -P 96"
alias qs4 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; ps; qbf -P 96"
alias qs5 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; ps; qbf -P 96"
alias qs6 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; ps; qbf -P 96"
alias qs7 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; ps; qbf -P 96"
alias qs8 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; ps; qbf -P 96"
alias qs9 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; ps; qbf -P 96"
alias qsA "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; qvar -I 105 -u; ps; qbf -P 96"
alias chnew "st; haig_start; resyn2; haig_use"
alias chnewrs "st; haig_start; resyn2rs; haig_use"
alias stdsd "r test/6in.blif; st; ps; u; bdd; dsd -g; st; ps"
alias trec "rec_start; r c.blif; st; rec_add; rec_use"
alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use"
alias trec5 "rec_start -K 5; r i10.blif; st; rec_add; rec_use"
alias trec6 "rec_start -K 6; r i10.blif; st; rec_add; rec_use"
alias trec7 "rec_start -K 7; r i10.blif; st; rec_add; rec_use"
alias trec8 "rec_start -K 8; r i10.blif; st; rec_add; rec_use"
alias trec10 "rec_start -K 10; r i10.blif; st; rec_add; rec_use"
alias trec12 "rec_start -K 12; r i10.blif; st; rec_add; rec_use"
#alias tsh "r i10_if.blif; st; ps; u; sw; st; ps; cec"
alias tst4 "r i10_if4.blif; st; ps; r x/rec4_.blif; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst4n "r i10_if4.blif; st; ps; r 5npn/all_functions.aig; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst6 "r i10_if6.blif; st; ps; r x/rec6_16_.blif; st; rec_start; r i10_if6.blif; st -r; ps; cec"
#alias t "r c.blif; st; wc c.cnf"
#alias t "r test/dsdmap6.blif; lutpack -vw; cec"
#alias t "r i10_if4.blif; lp"
#alias t1 "r pj1_if4.blif; lp"
#alias t2 "r pj1_if6.blif; lp"
#alias t "r pj/pj1.blif; st; dfraig -v"
#alias t "r c/16/csat_2.bench; st; dfraig -C 100 -v -r"
#alias t "r c/16/csat_147.bench; st; dfraig -C 10 -v -r"
#alias t "r i10.blif; st; ps; csweep; ps; cec"
#alias t "r c/5/csat_777.bench; st; csweep -v"
#alias t "r i10.blif; st; drw -v"
alias t "r c.blif; st; drf"
regression/issue_00174/abc.tcl 0 → 100644
source abc.rc;
print_lut;
resyn;
regression/issue_00174/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [5:0] o;
reg [5:0] i;
wire [5:0] wave_out;
always @(posedge clk)
i <= i + 1;
wire [31:0] w = 1-i;
assign wave_out = w/2;
top uut (i,o);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],wave_out[index]);
end
endgenerate
endmodule
regression/issue_00174/top.v 0 → 100644
module top
(
input [5:0] ptr,
output [5:0] wave_out
);
wire [31:0] w = 1-ptr;
assign wave_out = w/2;
endmodule
regression/issue_00175/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire GC;
wire GC_p;
reg E = 0;
always @(posedge clk)
E = ~E;
reg ED;
always@(*) begin
if(~clk)
ED = E;
end
assign GC_p = clk & ED;
top uut (clk,CG,E);
assert_dff check_output(clk,GC,GC_p);
endmodule
regression/issue_00175/top.v 0 → 100644
module top (
C,
GC,
E
);
input C;
output GC;
input E;
reg ED;
always@(*) begin
if(~C)
ED = E;
end
assign GC = C & ED;
endmodule
regression/issue_00182/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
endmodule
regression/issue_00183/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire out;
top uut (clk,out);
assert_dff check_output (clk,out,1'b1);
endmodule
regression/issue_00183/top.v 0 → 100644
module top(input in,output out);
SB_DFF dff(out,in,1);
endmodule
regression/issue_00186/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] adr = 0;
reg [1:0] din = 0;
wire [1:0] q;
reg mem_init = 0;
always @(posedge clk) begin
#3;
din <= din + 1;
adr <= adr + 1;
end
always @(posedge adr) begin
#10;
if(adr == 2'b11)
mem_init <= 1;
end
top uut (adr,clk,din,q);
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .A(q));
endmodule
module uut_mem_checker(input clk, input init, input [1:0] A);
always @(posedge clk)
begin
#1;
if (init == 1 & A === 2'bXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00186/top.v 0 → 100644
`define TEST_1
module top (
input [1:0] adr,
input clk,
input [1:0] din,
output reg [1:0] q
);
reg [1:0] ram [3:0];
always@(posedge clk)
begin
`ifdef TEST_1
{ram[adr],q} <= {din, ram[adr]};
`elsif TEST_2
ram[adr] <= din;
q <= ram[adr];
`endif
end
endmodule
regression/issue_00194/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire out;
top uut (clk,out);
assert_dff check_output (clk,out,1'b1);
endmodule
regression/issue_00194/top.v 0 → 100644
module top(input a, output y);
demo_sub sub (y, , 1'b1, a);
endmodule
module demo_sub(output y, z, input a, b);
assign y = a & b, z = a | b;
endmodule
regression/issue_00195/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00195/top.v 0 → 100644
module top(b);
input b;
wire a = 100_000.0;
endmodule
regression/run.sh
......@@ -2,41 +2,55 @@
set -ex
test -d $1
if [ "$2" != "verify" -a "$2" != "falsify" ]; then
test -f scripts/$2.ys
fi
test -f scripts/$2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
if [ "$2" = "verify" ]; then
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
elif [ "$2" = "falsify" ]; then
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
else
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v) ../../../../../techlibs/xilinx/brams_bb.v
fi
iverilog_adds=""
if [ "$2" = "falsify" ]; then
if vvp -N testbench > testbench.log 2>&1; then
echo FAIL > ${1}_${2}.status
elif ! grep 'ERROR' testbench.log || grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
# cases where 'syntax error' is expected
if [ "$1" = "issue_00089" ] ||\
[ "$1" = "issue_00093" ] ||\
[ "$1" = "issue_00095" ] ||\
[ "$1" = "issue_00096" ]; then
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
if grep 'syntax error' yosys.log; then
echo pass > ${1}_${2}.status
else
echo fail > ${1}_${2}.status
fi
fi
# cases with simulation checks
else
#Additional sources for iverilog simulation
if [ "$1" = "issue_00084" ]; then
iverilog_adds="../../../../../techlibs/xilinx/brams_bb.v"
elif [ "$1" = "issue_00160" ] ||\
[ "$1" = "issue_00182" ] ||\
[ "$1" = "issue_00183" ]; then
iverilog_adds="../../../../../techlibs/ice40/cells_sim.v"
fi
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v $iverilog_adds
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
echo fail > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
fi
touch .stamp
regression/scripts/issue_00114.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00126.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00128.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00132.ys 0 → 100644
read_verilog -defer ../top.v
chparam -set incr 42 topmod
synth -top top
write_verilog synth.v
regression/scripts/issue_00133.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00134.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
write_verilog -noexpr -norename synth.v
regression/scripts/issue_00160.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -top top
write_verilog synth.v
regression/scripts/issue_00171.ys 0 → 100644
read_verilog ../top.v
proc; opt; fsm; opt; memory; opt; techmap; opt
scc -all_cell_types
#and then put each found SCC into a module using submod.
scc -all_cell_types
synth -top top
write_verilog synth.v
regression/scripts/issue_00173.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00174.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
write_verilog -noattr t1.v
proc
opt -full
techmap
abc -lut 6
synth -top top
write_verilog synth.v
regression/scripts/issue_00175.ys 0 → 100644
read_verilog ../top.v
hierarchy
proc
opt
memory
opt
fsm
setundef -zero
opt -full -fine
setundef -zero
opt -full -fine
synth -top top
write_verilog synth.v
regression/scripts/issue_00182.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -blif litescope.bli -top top
write_verilog synth.v
regression/scripts/issue_00183.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -top top -blif test.blif
write_verilog synth.v
regression/scripts/issue_00186.ys 0 → 100644
read_verilog -DTEST_1 ../top.v
hierarchy -top top
proc
memory
opt -full
techmap
write_verilog -noattr synth.v
regression/scripts/issue_00194.ys 0 → 100644
read_verilog ../top.v
proc
prep -flatten
write_verilog synth.v
regression/scripts/issue_00195.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
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