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yosys-tests
Commit eb937aff by SergeyDegtyar
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Add tests for "IV frontends" tasklist 

IV frontends
=============

For frontends idea is that you do not do read_verilog but some you are
reading input in different format.
Since most of formats yosys can also read and write you can use plain
verilog write blif for example
and use that as source for this coverage. For liberty files many
examples can be found so that is also in list of tasks

1.
http://scratch.clifford.at/coverage_html/frontends/blif/blifparse.cc.gcov.html
2.
http://scratch.clifford.at/coverage_html/frontends/ilang/ilang_frontend.cc.gcov.html
3.
http://scratch.clifford.at/coverage_html/frontends/json/jsonparse.cc.gcov.html
4.
http://scratch.clifford.at/coverage_html/frontends/liberty/liberty.cc.gcov.html
parent f7c7f7c7
Showing with 3738 additions and 0 deletions
frontends/.gitignore 0 → 100644
/alu/work_*/
/.stamp
frontends/Makefile 0 → 100644
all: work
touch .stamp
clean::
rm -f .stamp
define template
$(foreach design,$(1),
$(foreach script,$(2),
work:: $(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp:
bash run.sh $(design) $(script)
clean::
rm -rf $(design)/work_$(script)
))
endef
#read_blif
$(eval $(call template,read_blif,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_and_or,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_fsm,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_logic,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_mem,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_mux,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_pmux,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_tri,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_eblif,read_blif_eblif))
#read_ilang
$(eval $(call template,read_ilang,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_fsm,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_mem,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_mux,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_tri,read_ilang read_ilang_selected))
#read_json
$(eval $(call template,read_json,read_json))
$(eval $(call template,read_json_fsm,read_json))
$(eval $(call template,read_json_logic,read_json))
$(eval $(call template,read_json_mem,read_json))
$(eval $(call template,read_json_mux,read_json))
$(eval $(call template,read_json_tri,read_json))
#read_liberty read_liberty_lib
$(eval $(call template,read_liberty,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_arith,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff_np,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff_pn,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff_pp,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_latch,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_latch_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_diff_inv,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_tri,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
.PHONY: all clean
frontends/common.v 0 → 100644
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
frontends/read_blif/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
frontends/read_blif/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_blif_and_or/testbench.v 0 → 100644
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_comb out_test(.A(patt_B), .B(B));
endmodule
frontends/read_blif_and_or/top.v 0 → 100644
module top
(
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_blif_eblif/eblif.eblif 0 → 100644
.model top
.names a b
.inputs a
.outputs b
.conn a b
.names a b c
11 1
.cname $my_and_gate
.latch a_and_b dff_q re clk 0
.attr src my_design.v:42
.end
frontends/read_blif_eblif/testbench.v 0 → 100644
module testbench;
reg a;
wire b = 1'bx;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.a(a),
.b(b)
);
assert_comb b_test(.A(1'bx),.B(b));
endmodule
frontends/read_blif_fsm/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_blif_fsm/top.v 0 → 100644
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
frontends/read_blif_logic/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
frontends/read_blif_logic/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg A1,cout1;
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A1 <= ~y + &cin;
end
always @(posedge x) begin
cout1 <= cin ? |y : ^A;
end
always @(posedge x) begin
A <= A1|y~&cin~^A1;
end
always @(posedge x) begin
cout <= cout1&cin~|y;
end
`else
assign {cout,A} = 1'bZ;
`endif
endmodule
frontends/read_blif_logic/top_clean.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_blif_mem/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_blif_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
parameter WIDTH=8;
// Declare the RAM variable
reg [WIDTH-1:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
frontends/read_blif_mux/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_blif_mux/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
parameter dw=4;
input[1:0] S;
input[dw-1:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[dw-1:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 #(4) u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/read_blif_pmux/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] S = 0;
wire [3:0] Y;
top uut (
.C (clk),
.S (S ),
.Y (Y )
);
always @(posedge clk) begin
//#3;
S <= S + 1;
end
assert_tri m16_test(.en(clk), .A(1'b1), .B(Y[0]|Y[1]|Y[2]|Y[3]));
endmodule
frontends/read_blif_pmux/top.v 0 → 100644
module top(C, S, Y);
input C;
input [1:0] S;
output reg [3:0] Y;
initial Y = 0;
always @(posedge C) begin
case (S)
2'b00: Y <= 4'b0001;
2'b01: Y <= 4'b0010;
2'b10: Y <= 4'b0100;
2'b11: Y <= 4'b1000;
endcase
end
endmodule
frontends/read_blif_tri/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
frontends/read_blif_tri/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
frontends/read_ilang/testbench.v 0 → 100644
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_comb out_test(.A(patt_B), .B(B));
endmodule
frontends/read_ilang/top.v 0 → 100644
module top
(
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_ilang_fsm/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_ilang_fsm/top.v 0 → 100644
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
frontends/read_ilang_mem/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clka(clk),
.clkb(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_ilang_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
frontends/read_ilang_mux/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_ilang_mux/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/read_ilang_tri/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
frontends/read_ilang_tri/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
frontends/read_json/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
frontends/read_json/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_json_fsm/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_json_fsm/top.v 0 → 100644
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
frontends/read_json_logic/testbench.v 0 → 100644
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_comb out_test(.A(patt_B), .B(B));
endmodule
frontends/read_json_logic/top.v 0 → 100644
module top
(
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_json_mem/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clka(clk),
.clkb(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_json_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
frontends/read_json_mux/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_json_mux/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/read_json_tri/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
frontends/read_json_tri/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
frontends/read_liberty/lib.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty/testbench.v 0 → 100644
module testbench;
reg a;
wire b = 1'bx;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.Y(b)
);
assert_comb b_test(.A(~a),.B(b));
endmodule
frontends/read_liberty_arith/lib.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
cell(top) {
pin(regA) {
direction : output ;
capacitance : 0.001;
function : "(y | x & cin)";
}
pin(regcout) {
direction : inout ;
capacitance : 0.001;
function : "(y + x & cin ^ regA)";
}
pin(x) {
direction : input ;
max_transition : 2.5;
capacitance : 0.001;
}
pin(y) {
direction : input ;
max_transition : 2.5;
capacitance : 0.001;
}
pin(cin) {
direction : input ;
max_transition : 2.5;
capacitance : 0.001;
}
}
}
frontends/read_liberty_arith/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.regA(out),
.regcout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
frontends/read_liberty_diff_inv/lib.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
cell_footprint : inv;
area : 129.6;
cell_leakage_power : 0.0310651;
pin(A) {
direction : input;
capacitance : 0.0159685;
rise_capacitance : 0.0159573;
fall_capacitance : 0.0159685; }
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.394734;
function : "(!A)";
timing() {
related_pin : "A";
timing_sense : negative_unate;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.147955, 0.218038, 0.359898, 0.922746, 1.76604", \
"0.224384, 0.292903, 0.430394, 0.991288, 1.83116", \
"0.365378, 0.448722, 0.584275, 1.13597, 1.97017", \
"0.462096, 0.551586, 0.70164, 1.24437, 2.08131", \
"0.756459, 0.874246, 1.05713, 1.62898, 2.44989"); }
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( ... ); }
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( ... ); }
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( ... ); }
} /* end timing */
internal_power() {
related_pin : "A";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( ... ); }
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( ... ); }
} /* end internal_power */
} /* end Pin Y */
} /* end INVX1 */
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_diff_inv/testbench.v 0 → 100644
module testbench;
reg a;
wire b = 1'bx;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.Y(b)
);
assert_comb b_test(.A(~a),.B(b));
endmodule
frontends/read_liberty_ff/lib.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "dff";
ff("IQ", "IQN") {
next_state : " D ";
clocked_on : " CLK ";
clear : " CLR ";
}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_ff/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_ff_n/lib.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "dff";
ff("IQ", "IQN") {
next_state : " D ";
clocked_on : " CLK ";
clear : " CLR ";
preset : " PRE ";
}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( PRE ) {
direction : input;
capacitance : 0.0135;
} /* end of pin PRE */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
timing () { /* propagation delay from falling edge of preset to Q=1 */
timing_type : preset;
timing_sense : negative_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "PRE";
} /* end of Q timing related to PRE */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_ff_n/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_ff_np/lib.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "dff";
ff("IQ", "IQN") {
next_state : " D ";
clocked_on : " CLK ";
clear : " CLR ";
preset : " PRE ";
}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( PRE ) {
direction : input;
capacitance : 0.0135;
} /* end of pin PRE */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : negative_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
timing () { /* propagation delay from falling edge of preset to Q=1 */
timing_type : preset;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "PRE";
} /* end of Q timing related to PRE */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_ff_np/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_ff_pn/lib.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "dff";
ff("IQ", "IQN") {
next_state : " D ";
clocked_on : " CLK ";
clear : " CLR ";
preset : " PRE ";
}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( PRE ) {
direction : input;
capacitance : 0.0135;
} /* end of pin PRE */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
timing () { /* propagation delay from falling edge of preset to Q=1 */
timing_type : preset;
timing_sense : negative_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "PRE";
} /* end of Q timing related to PRE */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_ff_pn/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_ff_pp/lib.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "dff";
ff("IQ", "IQN") {
next_state : " D ";
clocked_on : " CLK ";
clear : " CLR ";
preset : " PRE ";
}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( PRE ) {
direction : input;
capacitance : 0.0135;
} /* end of pin PRE */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
timing () { /* propagation delay from falling edge of preset to Q=1 */
timing_type : preset;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "PRE";
} /* end of Q timing related to PRE */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_ff_pp/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_latch/lib.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
data_in : "D" ;
clear : "CLR" ;}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_latch/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_latch_n/lib.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
data_in : "D" ;
preset : "CLR" ;}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_falling;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_falling;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : falling_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : preset;
timing_sense : negative_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_latch_n/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_tri/lib.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
/* Enabled inverter or tristate inverter */
cell(top) {
area : 324;
cell_footprint : "eninv";
pin(A) {
direction : input;
capacitance : 0.027;
} /* end of pin A */
pin(En) {
direction : input;
capacitance : 0.0135;
} /*end of pin En */
pin(Y) {
direction : output;
function : "A";
three_state : "En";
timing () {
timing_sense : negative_unate;
related_pin : "A";
cell_rise(lu5x5) { values( " ... " );}
rise_transition(lu5x5) { values( " ... " );}
cell_fall(lu5x5) { values( " ... " );}
fall_transition(lu5x5) { values( " ... " );}
} /* end of enabled timing */
timing() {
timing_sense : positive_unate;
timing_type : three_state_enable;
related_pin : "En";
cell_rise(delay_template_5x5) { values( " ... " );}
rise_transition(delay_template_5x5) { values( " ... " );}
cell_fall(delay_template_5x5) { values( " ... " );}
fall_transition(delay_template_5x5) { values( " ... " );}
} /* end of enable timing */
timing() {
timing_sense : negative_unate;
timing_type : three_state_disable;
related_pin : "En";
cell_rise(delay_template_5x1) { values( " ... " );}
rise_transition(delay_template_5x1) { values( " ... " );}
cell_fall(delay_template_5x1) { values( " ... " );}
fall_transition(delay_template_5x1) { values( " ... " );}
} /* end of disable timing */
} /* end of pin Y */
} /* end of eninv */
}
frontends/read_liberty_tri/testbench.v 0 → 100644
module testbench;
reg a;
reg En = 1'b1;
wire b = 1'bx;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.En(En),
.Y(b)
);
assert_comb b_test(.A(a),.B(b));
endmodule
frontends/run.sh 0 → 100644
#!/bin/bash
set -ex
test -d $1
test -f scripts/$2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
yosys -ql yosys.log ../../scripts/$2.ys
sed -i 's/reg =/dummy =/' ./synth.v
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
touch .stamp
frontends/scripts/read_blif.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_attr.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -attr blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_buf.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -buf a a a blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_cname.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -cname blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_conn.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -conn blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_eblif.ys 0 → 100644
read_blif -wideports ../eblif.eblif
synth -top top
write_verilog synth.v
frontends/scripts/read_blif_param.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -param blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_sop.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -sop blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_wideports.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -wideports blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_ilang.ys 0 → 100644
read_verilog ../top.v
proc
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang ilang.ilang
dump -n -o file1.il
write_verilog synth.v
frontends/scripts/read_ilang_selected.ys 0 → 100644
read_verilog ../top.v
proc
dump -o file.il
write_ilang -selected ilang.ilang
design -reset
read_ilang ilang.ilang
dump -n -o file1.il
write_verilog synth.v
frontends/scripts/read_json.ys 0 → 100644
read_verilog ../top.v
write_json json.json
design -reset
read_json json.json
write_verilog synth.v
frontends/scripts/read_liberty.ys 0 → 100644
read_liberty -lib ../lib.lib
design -reset
read_liberty ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_ignore_miss_data_latch.ys 0 → 100644
read_liberty -ignore_miss_data_latch ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_ignore_miss_dir.ys 0 → 100644
read_liberty -ignore_miss_dir ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_ignore_miss_func.ys 0 → 100644
read_liberty -ignore_miss_func ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_lib.ys 0 → 100644
read_liberty -lib ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_nooverwrite.ys 0 → 100644
read_liberty -nooverwrite ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_setattr.ys 0 → 100644
read_liberty -setattr a ../lib.lib
synth -top top
write_verilog synth.v
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