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yosys-tests
Commit c6a08d25 by SergeyDegtyar
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Add tests for issues 196-444

parent 461b4673
Showing with 1658 additions and 5 deletions
regression/Makefile
......@@ -147,5 +147,71 @@ $(eval $(call template,issue_00194,issue_00194))
#issue_00195
$(eval $(call template,issue_00195,issue_00195))
#issue_00196
$(eval $(call template,issue_00196,issue_00196))
#issue_00210
$(eval $(call template,issue_00210,issue_00210))
#issue_00253
$(eval $(call template,issue_00253,issue_00253))
#issue_00282
$(eval $(call template,issue_00282,issue_00282))
#issue_00283
$(eval $(call template,issue_00283,issue_00283))
#issue_00287
$(eval $(call template,issue_00287,issue_00287))
#issue_00289
$(eval $(call template,issue_00289,issue_00289))
#issue_00291
$(eval $(call template,issue_00291,issue_00291))
#issue_00300
$(eval $(call template,issue_00300,issue_00300))
#issue_00306
$(eval $(call template,issue_00306,issue_00306))
#issue_00314
$(eval $(call template,issue_00314,issue_00314))
#issue_00317
$(eval $(call template,issue_00317,issue_00317))
#issue_00341
$(eval $(call template,issue_00341,issue_00341))
#issue_00342
$(eval $(call template,issue_00342,issue_00342))
#issue_00349
$(eval $(call template,issue_00349,issue_00349))
#issue_00350
$(eval $(call template,issue_00350,issue_00350))
#issue_00361
$(eval $(call template,issue_00361,issue_00361))
#issue_00362
$(eval $(call template,issue_00362,issue_00362))
#issue_00372
$(eval $(call template,issue_00372,issue_00372))
#issue_00391
$(eval $(call template,issue_00391,issue_00391))
#issue_00432
$(eval $(call template,issue_00432,issue_00432))
#issue_00444
$(eval $(call template,issue_00444,issue_00444))
.PHONY: all clean
regression/issue_00196/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire a,b,c,d,e,f;
top uut(clk,a,b,c,d,e,f);
endmodule
regression/issue_00196/top.v 0 → 100644
module top(p1h, p1l, p2h, p2l, p3h, p3l);
(* LOC="P3" *) output p1h;
(* LOC="P4" *) output p1l;
(* LOC="P5" *) output p2h;
(* LOC="P6" *) output p2l;
(* LOC="P7" *) output p3h;
(* LOC="P8" *) output p3l;
wire clk;
GP_LFOSC #(
.AUTO_PWRDN(0),
.OUT_DIV(1)
) osc (
.CLKOUT(clk)
);
localparam DIVIDER = 1;//400;
reg [13:0] divcnt = DIVIDER;
always @(posedge clk)
if(divcnt == 0)
divcnt <= DIVIDER;
else
divcnt <= divcnt - 1;
wire reset;
GP_POR por(
.RST_DONE(reset)
);
reg [2:0] state;
always @(posedge divcnt or negedge reset)
if(!reset)
state <= 0;
else
case(state)
0: state <= 1;
1: state <= 2;
2: state <= 3;
3: state <= 4;
4: state <= 5;
5: state <= 0;
endcase
reg [5:0] phases;
always @(*) begin
phases <= 6'b000000;
case(state)
0: phases <= 6'b100100;
1: phases <= 6'b000110;
2: phases <= 6'b010010;
3: phases <= 6'b011000;
4: phases <= 6'b001001;
5: phases <= 6'b100001;
endcase
end
wire p1i, p2i, p3i;
assign {p1i, p1l, p2i, p2l, p3i, p3l} = phases;
assign {p1h, p2h, p3h} = ~{p1i, p2i, p3i};
endmodule
regression/issue_00210/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [9:0] a;
top uut(a);
endmodule
regression/issue_00210/top.v 0 → 100644
module top(result);
output signed [9:0] result;
wire signed [9:0] intermediate [0:2];
function integer depth2Index;
input integer depth;
depth2Index = depth;
endfunction
assign intermediate[depth2Index(2)] = 0;
assign result = intermediate[2];
endmodule
regression/issue_00253/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] in = 2;
reg [1:0] count = 0;
reg init = 0;
wire [7:0] out;
always @(posedge clk)
begin
in = in + 7;
count = count + 1;
if (count == 2'b11)
init = 1;
end
top uut(clk,in,out);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
check_X check_output(clk,init,out[index]);
end
endgenerate
endmodule
module check_X(input clk,input init, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX && init == 1'b1)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00282/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] in = 2;
reg [1:0] count = 0;
reg init = 0;
wire [7:0] out;
always @(posedge clk)
begin
in = in + 7;
count = count + 1;
if (count == 2'b11)
init = 1;
end
top uut(clk,in,out);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
check_X check_output(clk,init,out[index]);
end
endgenerate
endmodule
module check_X(input clk,input init, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX && init == 1'b1)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00283/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire y;
top uut(clk,1'b1,y);
assert_X check_output(clk,y);
endmodule
regression/issue_00283/top.v 0 → 100644
module top(input clk, enable, output reg y);
wire [1:0] foo [1:0];
integer i;
initial begin
for (i=0;i<=1;i=i+1)
foo[i] = 2'b11;
end
always @(posedge clk)
if (enable)
for (i = 0; i < 2; i=i+1)
y <= foo[0][0];
endmodule
regression/issue_00287/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [6:0] D = 0;
reg [1:0] S = 0;
wire [1:0] Y;
reg [1:0] Y_p;
always @(posedge clk)
begin
D = D + 3;
S = S + 1;
end
always @* begin : block
reg [3:0] data [0:3];
data[0] = D[3:0];
data[1] = D[4:1];
data[2] = D[5:2];
data[3] = D[6:3];
Y_p = data[S];
end
top uut(D,S,Y);
assert_dff check_Y0 (clk,Y[0],Y_p[0]);
assert_dff check_Y1 (clk,Y[1],Y_p[1]);
endmodule
regression/issue_00287/top.v 0 → 100644
module top(input [6:0] D, input [1:0] S, output reg [1:0] Y);
always @* begin : block
reg [3:0] data [0:3];
data[0] = D[3:0];
data[1] = D[4:1];
data[2] = D[5:2];
data[3] = D[6:3];
Y = data[S];
end
endmodule
regression/issue_00289/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire o;
top uut(clk,o);
assert_dff check_o (clk,clk,o);
endmodule
regression/issue_00289/top.v 0 → 100644
function f(input i);
reg [1:0] mem0 [1:0];
f = i;
endfunction
module top(in,out);
input in;
output out;
assign out = f(in);
endmodule
regression/issue_00291/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 0;
reg any_pop = 0;
reg any_push = 0;
always @(posedge clk)
begin
rst = 1;
#1
any_pop = ~any_pop;
#3
any_push = ~any_push;
end
top uut(rst,clk,any_push,any_pop);
endmodule
regression/issue_00291/top.v 0 → 100644
module top (
input reset,
input clk,
input any_push,
input any_pop
);
reg [1:0] fifo_head [3:0];
reg [1:0] fifo_next [3:0];
wire [1:0] fifo_head4samp [3:0];
genvar fifo_num ;
integer pntr_num,fifoifo_num;
generate
for (fifo_num=0; fifo_num<4; fifo_num=fifo_num+1) begin:fifo_gen
assign fifo_head4samp[fifo_num] = fifo_next[fifo_head[fifo_num]] ; /* this is line 16 */
end
endgenerate
always @(posedge clk or negedge reset)
begin
if (!reset) begin
for (pntr_num=0; pntr_num<4; pntr_num=pntr_num+1)
fifo_next[pntr_num] <= {2{1'b0}} ;
end
else if (any_push | any_pop) begin
for (fifoifo_num=0; fifoifo_num<4; fifoifo_num=fifoifo_num+1) begin
fifo_head[fifoifo_num] <= fifo_head4samp[fifoifo_num] ;
end
end
end
endmodule
regression/issue_00300/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] addr = 0;
reg [7:0] wdata = 0;
wire [7:0] rdata;
wire [7:0] rdata_o;
always @(posedge clk)
begin
addr = addr + 1;
wdata = wdata + 17;
end
reg [7:0] memory [255:0];
assign rdata = memory[addr];
always @(posedge clk) memory[addr] <= wdata;
top uut(clk,addr,wdata,rdata_o);
uut_mem_checker port_b_test(.clk(clk), .A(rdata), .B(rdata_o));
endmodule
module uut_mem_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A == B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00300/top.v 0 → 100644
module top(input clk, input [7:0] addr, wdata, output [7:0] rdata);
reg [7:0] memory [255:0];
assign rdata = memory[addr];
always @(posedge clk) memory[addr] <= wdata;
endmodule
regression/issue_00306/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] a = 0;
wire res_p;
wire res;
always @(posedge clk)
begin
a = a + 1;
end
assign res_p = a < 6'b100000;
top uut(a,res);
assert_dff check_res (clk,res, res_p);
endmodule
regression/issue_00306/top.v 0 → 100644
module top (input [3:0] a, output res);
assign res = a < 6'b100000;
endmodule
regression/issue_00314/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
reg [7:0] b = 0;
wire [7:0] z;
always @(posedge clk)
begin
a = a + 1;
b = b + 7;
end
top uut(a,b,z);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,z[index]);
end
endgenerate
endmodule
regression/issue_00314/top.v 0 → 100644
module top(a,b,z);
parameter width_a = 8;
parameter width_b = 8;
input [width_a-1:0] a;
input [width_b-1:0] b;
output [width_a-1:0] z;
reg [width_a-1:0] z;
always@(a or b)
begin
div_u(a,b,z);
end
function [width_b:0] minus;
input [width_b:0] in1;
input [width_b:0] in2;
minus = in1 - in2;
endfunction
task divmod;
input [width_a-1:0] l;
input [width_b-1:0] r;
output [width_a-1:0] rdiv;
output [width_b-1:0] rmod;
parameter llen = width_a;
parameter rlen = width_b;
reg [(llen+rlen)-1:0] lbuf;
reg [rlen:0] diff;
integer i;
begin
lbuf = 0;
lbuf[llen-1:0] = l;
for(i=width_a-1;i>=0;i=i-1)
begin
diff = minus(lbuf[(llen+rlen)-1:llen-1], {1'b0,r});
rdiv[i] = ~diff[rlen];
if(diff[rlen] == 0)
lbuf[(llen+rlen)-1:llen-1] = diff;
lbuf[(llen+rlen)-1:1] = lbuf[(llen+rlen)-2:0];
end
rmod = lbuf[(llen+rlen)-1:llen];
end
endtask
task div_u;
input [width_a-1:0] l;
input [width_b-1:0] r;
output [width_a-1:0] rdiv;
reg [width_a-01:0] rdiv; // <-- this line causes problem
reg [width_b-1:0] rmod;
begin
divmod(l, r, rdiv, rmod);
end
endtask
endmodule
regression/issue_00317/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00317/top.v 0 → 100644
module top(
alu_data_d_in,
alu_data_d_out
);
input [7:0]alu_data_d_in;
output[7:0]alu_data_d_out;
wire [7:0]swap_out;
genvar i;
generate
for ( i = 7 ; ( i >= 4 ) ; i-- )
begin : swap_h
assign swap_out[i] = alu_data_d_in[( ( i - 4 ) )];
end
endgenerate
generate
for ( i = 0 ; ( i <4 ) ; i++ )
begin : swap_l
assign swap_out[i] = alu_data_d_in[(i+4 )];
end
endgenerate
assign alu_data_d_out = swap_out;
endmodule
regression/issue_00341/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i1,i2 = 0;
wire o1g,o2g;
wire o1r,o2r;
wire o1w,o2w;
wire o1gt,o2gt;
wire o1rt,o2rt;
wire o1wt,o2wt;
always @(posedge clk) begin
i1 <= i1 + 1;
i2 <= i2 + 1;
end
gold uut_g (
i1,i2,o1g,o2g
);
top_r uut_r (
i1,i2,o1r,o2r
);
top_w uut_w (
i1,i2,o1w,o2w
);
goldt uut_gt (
i1,i2,o1gt,o2gt
);
top_rt uut_rt (
i1,i2,o1rt,o2rt
);
top_wt uut_wt (
i1,i2,o1wt,o2wt
);
assert_dff gold_test(clk,o1g,o1gt);
assert_dff top_r_test(clk,o1r,o1rt);
assert_dff top_w_test(clk,o1w,o1wt);
endmodule
module goldt(input i1, input i2, output o2, output o1);
wire _1_;
assign o2 = i1 & i2;
assign _1_ = i1 | i2;
assign o1 = _1_ & o2;
endmodule
module top_rt( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 && i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
module top_wt( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 & i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
regression/issue_00341/top.v 0 → 100644
module gold(input i1, input i2, output o2, output o1);
wire _1_;
assign o2 = i1 & i2;
assign _1_ = i1 | i2;
assign o1 = _1_ & o2;
endmodule
module top_r( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 && i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
module top_w( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 & i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
regression/issue_00342/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] addr = 0;
reg [7:0] wdata = 0;
wire [7:0] rdata;
wire [7:0] rdata_o;
always @(posedge clk)
begin
addr = addr + 1;
wdata = wdata + 17;
end
logic [8-1:0] mem [8-1:0];
assign rdata_o = mem[addr];
always @*
if (clk)
mem[addr] <= wdata;
top uut(rdata,wdata,addr,clk,clk);
uut_mem_checker port_b_test(.clk(clk), .A(rdata), .B(rdata_o));
endmodule
module uut_mem_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00342/top.v 0 → 100644
`timescale 1ns / 1ns
module top #(parameter AWIDTH=8,
localparam DEPTH=1<<AWIDTH,
parameter DWIDTH=8)
(output [DWIDTH-1:0] rdata,
input [DWIDTH-1:0] wdata,
input [AWIDTH-1:0] addr,
input r_wn, cs_n);
logic [DWIDTH-1:0] mem [DEPTH];
assign rdata = mem[addr];
always_latch
if (!cs_n && !r_wn) mem[addr] <= wdata;
endmodule
regression/issue_00349/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
reg z_p;
wire z;
always @(posedge clk) begin
in <= in + 1;
end
always @*
z_p <= in[0] ~& in[1];
top uut (in[0],in[1],z);
assert_dff z_test(clk,z,z_p);
endmodule
regression/issue_00349/top.v 0 → 100644
module top (input wire x, input wire y, output reg z);
always @*
z <= x ~& y;
endmodule
regression/issue_00350/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i;
wire o_p;
wire o;
always @(posedge clk) begin
#2
i <= ~i;
end
reg q = 0;
always @(posedge clk) q <= 1;
assign o_p = q & i;
top uut (clk,i,o);
assert_dff z_test(clk,o,o_p);
endmodule
regression/issue_00350/top.v 0 → 100644
module top (input clk, input i, output o);
reg q = 0;
always @(posedge clk) q <= 1;
assign o = q & i;
endmodule
regression/issue_00361/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] A, B, C, D = 0;
reg [127:0] E, F = 0;
reg [127:0] X_p, Y_p;
wire [127:0] X,Y;
always @(posedge clk)
begin
A = A + 248;
B = B + 338;
C = C + 435;
D = D + 282;
E = E + 1248;
F = F + 2148;
end
integer i;
always @* begin
X_p = A*B + E;
Y_p = F;
for (i = 0; i < 64; i=i+1)
Y_p = Y_p + C[i]*D[i];
end
top uut (A,B,C,D,E,F,X,Y);
uut_checker X_test(.clk(clk), .A(X), .B(X_p));
uut_checker Y_test(.clk(clk), .A(Y), .B(Y_p));
endmodule
module uut_checker(input clk, input [127:0] A, input [127:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00361/top.v 0 → 100644
module top (input [63:0] A, B, C, D, input [127:0] E, F, output reg [127:0] X, Y);
integer i;
always @* begin
X = A*B + E;
Y = F;
for (i = 0; i < 64; i=i+1)
Y = Y + C[i]*D[i];
end
endmodule
regression/issue_00362/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] A, B, C, D = 0;
reg [127:0] E, F = 0;
reg [127:0] X_p, Y_p;
wire [127:0] X,Y;
always @(posedge clk)
begin
A = A + 248;
B = B + 338;
C = C + 435;
D = D + 282;
E = E + 1248;
F = F + 2148;
end
integer i;
always @* begin
X_p = A*B + E;
Y_p = F;
for (i = 0; i < 64; i=i+1)
Y_p = Y_p + C[i]*D[i];
end
top uut (A,B,C,D,E,F,X,Y);
uut_checker X_test(.clk(clk), .A(X), .B(X_p));
uut_checker Y_test(.clk(clk), .A(Y), .B(Y_p));
endmodule
module uut_checker(input clk, input [127:0] A, input [127:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00362/top.v 0 → 100644
module inst(a,b);
output b;
input a;
assign b = ~a;
endmodule
module top(a,b);
input a;
output b;
inst inst(
.a(a),
.b(1'b1)
);
endmodule
regression/issue_00372/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg d = 0;
wire q;
reg q_p = 0;
always @(posedge clk)
q_p <= d;
top uut (clk,d,q);
assert_dff q_test(clk,q,q_p);
endmodule
regression/issue_00372/top.v 0 → 100644
module top(clk,d,q);
input clk,d;
output reg q;
always @(posedge clk)
if (!1'h1)
q <= 0;
else
q <= d;
endmodule
regression/issue_00391/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (clk);
endmodule
regression/issue_00391/top.v 0 → 100644
module decode1_1(input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r_ready;
always @(posedge clk) begin
if (rst) begin
r_remaining_count <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
if (r_remaining_count == 0) begin
if (r_ready && in_valid) begin
r_remaining_count <= in_count;
r_valid <= in_count != 0;
r_ready <= 0;
end else begin
r_ready <= 1;
r_valid <= 0;
end
end else begin
r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
r_ready <= 0;
if (out_valid && out_ready) begin
r_remaining_count <= r_remaining_count - 1;
end
end
end
end
endmodule // decode1_1
module top(input clk);
wire out_valid;
wire [31:0] out_data;
wire out_ready = 1'b1;
reg [31:0] cycles;
wire rst = (cycles < 3);
wire in_ready;
reg [31:0] test_counts [0:1];
reg [31:0] test_index;
wire in_valid = (test_index < 1) && (cycles > 2);
reg [9:0] out_data_index;
always @(posedge clk)
begin
cycles <= cycles + 1;
end
always @(posedge clk)
begin
if (cycles < 1) begin
test_counts[cycles] <= $anyseq;
end
end
initial begin
cycles = 0;
test_index = 0;
end
decode1_1 decoder(clk, rst,
test_counts[test_index],
in_valid,
in_ready,
out_ready,
out_valid);
always @(posedge clk) begin
if (!rst) begin
assert(out_data_index <= 0);
if (in_valid && in_ready) begin
test_index <= test_index + 1;
end
if (out_ready && out_valid) begin
out_data_index <= out_data_index + 1;
end
end
end // always @ (posedge clk)
endmodule
regression/issue_00391/top_clean.v 0 → 100644
module decode1_1(input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r_ready;
always @(posedge clk) begin
if (rst) begin
r_remaining_count <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
if (r_remaining_count == 0) begin
if (r_ready && in_valid) begin
r_remaining_count <= in_count;
r_valid <= in_count != 0;
r_ready <= 0;
end else begin
r_ready <= 1;
r_valid <= 0;
end
end else begin
r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
r_ready <= 0;
if (out_valid && out_ready) begin
r_remaining_count <= r_remaining_count - 1;
end
end
end
end
endmodule // decode1_1
module top(input clk);
wire out_valid;
wire [31:0] out_data;
wire out_ready = 1'b1;
reg [31:0] cycles;
wire rst = (cycles < 3);
wire in_ready;
reg [31:0] test_counts [0:1];
reg [31:0] test_index;
wire in_valid = (test_index < 1) && (cycles > 2);
reg [9:0] out_data_index;
always @(posedge clk)
begin
cycles <= cycles + 1;
end
always @(posedge clk)
begin
if (cycles < 1) begin
//test_counts[cycles] <= $anyseq;
end
end
initial begin
cycles = 0;
test_index = 0;
end
decode1_1 decoder(clk, rst,
test_counts[test_index],
in_valid,
in_ready,
out_ready,
out_valid);
always @(posedge clk) begin
if (!rst) begin
// assert(out_data_index <= 0);
if (in_valid && in_ready) begin
test_index <= test_index + 1;
end
if (out_ready && out_valid) begin
out_data_index <= out_data_index + 1;
end
end
end // always @ (posedge clk)
endmodule
regression/issue_00432/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a;
reg [7:0] b;
wire [7:0] c_p;
wire [7:0] c;
always @(posedge clk)
begin
a = a + 3;
b = b + 7;
end
assign c_p = a[$signed(b) +: 8];
top uut (a, b, c);
uut_checker c_test(.clk(clk), .A(c_p), .B(c));
endmodule
module uut_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00432/top.v 0 → 100644
module top(a, b, c);
input [7:0] a;
input [7:0] b;
output [7:0] c;
assign c = a[$signed(b) +: 8];
endmodule
regression/issue_00444/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] a;
wire [31:0] c;
always @(posedge clk)
begin
a = a + 3;
end
top uut (clk, a, c);
uut_checker c_test(.clk(clk), .A(c), .B(c));
endmodule
module uut_checker(input clk, input [31:0] A, input [31:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00444/top.v 0 → 100644
`ifdef FORMAL
`define assume(_expr_) assume(_expr_)
`else
`define assume(_expr_)
`endif
module top(input clk, input [4:0] addr, output reg [31:0] data);
reg [31:0] mem [0:31];
always @(posedge clk)
data <= mem[addr];
reg [31:0] used_addr = 0;
reg [31:0] used_dbits = 0;
reg initstate = 1;
always @(posedge clk) begin
initstate <= 1;
if (!initstate) begin
//`assume(data != 0);
//`assume((used_dbits & data) == 0);
end
end
endmodule
regression/run.sh
......@@ -8,19 +8,27 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
iverilog_adds=""
# cases where 'syntax error' is expected
# cases where 'syntax error' or other errors are expected
if [ "$1" = "issue_00089" ] ||\
[ "$1" = "issue_00093" ] ||\
[ "$1" = "issue_00095" ] ||\
[ "$1" = "issue_00096" ]; then
[ "$1" = "issue_00096" ] ||\
[ "$1" = "issue_00196" ] ||\
[ "$1" = "issue_00362" ]; then
expected_string="syntax error"
#Change checked string for check other errors
if [ "$1" = "issue_00196" ]; then
expected_string="Found posedge/negedge event"
elif [ "$1" = "issue_00362" ]; then
expected_string="is connected to constants:"
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo fail > ${1}_${2}.status
else
if grep 'syntax error' yosys.log; then
if grep "$expected_string" yosys.log; then
echo pass > ${1}_${2}.status
else
echo fail > ${1}_${2}.status
......@@ -30,6 +38,7 @@ if [ "$1" = "issue_00089" ] ||\
# cases with simulation checks
else
iverilog_adds=""
#Additional sources for iverilog simulation
if [ "$1" = "issue_00084" ]; then
iverilog_adds="../../../../../techlibs/xilinx/brams_bb.v"
......
regression/scripts/issue_00196.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -json 3pdrive.json
write_verilog synth.v
regression/scripts/issue_00210.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00253.ys 0 → 100644
read_verilog ../top.v
proc; opt; fsm -encoding binary
techmap; opt; stat
write_verilog synth.v
regression/scripts/issue_00282.ys 0 → 100644
read_verilog ../top.v
synth -top top
#synth_ice40 -blif litescope.bli -top top
write_verilog synth.v
regression/scripts/issue_00283.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00287.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00289.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00291.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00300.ys 0 → 100644
read_verilog ../top.v
proc
opt
stat
dump
write_ilang foo.ilang
memory_collect
stat
dump t:$mem
design -reset
read_ilang foo.ilang
stat
memory_collect
dump t:$mem
write_verilog synth.v
regression/scripts/issue_00306.ys 0 → 100644
read_verilog ../top.v
proc
opt -full
synth -top top
write_verilog synth.v
regression/scripts/issue_00314.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00317.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00341.ys 0 → 100644
read_verilog ../top.v
equiv_make gold top_w equiv
hierarchy -top equiv
opt -purge
equiv_simple
equiv_status -assert
design -reset
read_verilog ../top.v
synth
write_verilog synth.v
regression/scripts/issue_00342.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00349.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00350.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
abc -clk clk -g AND
opt
write_verilog synth.v
regression/scripts/issue_00361.ys 0 → 100644
read_verilog -sv ../top.v
prep
alumacc
maccmap -unmap
synth -top top
write_verilog synth.v
regression/scripts/issue_00362.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00372.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00391.ys 0 → 100644
read_verilog -sv ../top.v
prep -top top -nordff
write_smt2 top.smt2
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00432.ys 0 → 100644
read_verilog -sv ../top.v
proc
hierarchy -check
synth -top top
write_verilog synth.v
regression/scripts/issue_00444.ys 0 → 100644
read_verilog -formal ../top.v
hierarchy
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
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