Add tests for MISC task list; Add test for write_table command

MISC
=====
Tasks in this group are just generating some output, so no traditional
test bench could be made. Writing output from yosys and checking if
result is expected is advised.

1.http://scratch.clifford.at/coverage_html/passes/tests/test_abcloop.cc.gcov.html
This represents some internal tests for ABC loops
2.
http://scratch.clifford.at/coverage_html/passes/tests/test_cell.cc.gcov.html
note that you need to provide multiple tests in order to cover testing
of all cell types. Also output should be checked if it contain "Fail" or
"Error" in it
3.
http://scratch.clifford.at/coverage_html/passes/cmds/torder.cc.gcov.html
Use some verilog file, do proc and this should display you all cells in
designed ordered. Require multiple different parameters to cover all.
4.http://scratch.clifford.at/coverage_html/passes/cmds/trace.cc.gcov.html
loading verilog file and doing  "trace proc" will create output with
additional logs, not much to check from output to be honest
5.
http://scratch.clifford.at/coverage_html/passes/cmds/write_file.cc.gcov.html
just write to file and check if written output is fine
6.
http://scratch.clifford.at/coverage_html/passes/cmds/stat.cc.gcov.html
if you have liberty cell library files, try it with those specified.
7.
http://scratch.clifford.at/coverage_html/passes/cmds/show.cc.gcov.html
note that you would always need to set -viewer since you do not wish to
call graphwiz.
Need covering of various parameters on a reasonable complicated design
to cover.
8. http://scratch.clifford.at/coverage_html/passes/cmds/scc.cc.gcov.html
detection of logic loops, output needs to be tested in order to check if
loop was detected on not.
9.
http://scratch.clifford.at/coverage_html/passes/cmds/scatter.cc.gcov.html
After doing synth on existing design, just run this step, can do
opt_clean after and there should be lot of temporary and unused wires
removed.
10.
http://scratch.clifford.at/coverage_html/passes/cmds/rename.cc.gcov.html
can load design and rename top modue, output should contain module with
new name
11.
http://scratch.clifford.at/coverage_html/passes/cmds/qwp.cc.gcov.html
Use it on simple design since it takes a while on big ones.
12.
http://scratch.clifford.at/coverage_html/passes/cmds/ltp.cc.gcov.html
Check if returns expected value for your design
13.
http://scratch.clifford.at/coverage_html/passes/cmds/edgetypes.cc.gcov.html
it just outputs report, so not sure what would be valid to check, just
execute for now.
14.
http://scratch.clifford.at/coverage_html/passes/cmds/delete.cc.gcov.html
load existing design and try removing inputs, outputs,... complete
design
15.
http://scratch.clifford.at/coverage_html/passes/cmds/cover.cc.gcov.html
it just prints report, so nothing to check

MISC/.gitignore

+*/work_*/
+/.stamp

MISC/Makefile

+all: work
+	touch .stamp
+
+clean::
+	rm -f .stamp
+
+define template
+$(foreach design,$(1),
+$(foreach script,$(2),
+work:: $(design)/work_$(script)/.stamp
+
+$(design)/work_$(script)/.stamp:
+	bash run.sh $(design) $(script)
+
+clean::
+	rm -rf $(design)/work_$(script)
+))
+endef
+
+#test_abcloop
+$(eval $(call template,test_abcloop,test_abcloop test_abcloop_n test_abcloop_s ))
+
+#test_cell
+#test_cell_map - takes a lot of time
+# test_cell_mux, test_cell_pmux - is not supported
+$(eval $(call template,test_cell,test_cell test_cell_aigmap test_cell_const test_cell_edges test_cell_f  test_cell_div test_cell_muxdiv test_cell_n test_cell_noeval test_cell_nosat test_cell_s test_cell_script test_cell_simlib test_cell_v test_cell_vlog test_cell_w test_cell_alu test_cell_sop test_cell_lut test_cell_macc test_cell_lcu test_cell_fa))
+
+#torder
+$(eval $(call template,torder,torder torder_stop torder_noautostop ))
+
+#trace
+$(eval $(call template,trace,trace ))
+
+#write_file
+$(eval $(call template,write_file,write_file write_file_a ))
+
+#stat
+$(eval $(call template,stat, stat stat_top stat_width stat_liberty ))
+
+#show
+# show_pause - skipped
+$(eval $(call template,show, show show_colorattr show_colors show_color show_enum show_format show_label show_lib show_long show_notitle show_prefix show_signed show_stretch show_viewer show_width))
+
+#scc
+$(eval $(call template,scc, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
+
+#scatter
+$(eval $(call template,scatter, scatter ))
+
+#rename
+$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat))
+
+#qwp
+#qwp_v - exception
+#+ yosys -ql yosys.log ../../scripts/qwp_v.ys
+#run.sh: line 11: 28262 Floating point exception(core dumped) yosys -ql yosys.log ../../scripts/$2.ys
+$(eval $(call template,qwp, qwp qwp_ltr qwp_grid qwp_dump qwp_alpha))
+
+#ltp
+$(eval $(call template,ltp, ltp ltp_noff ))
+
+#edgetypes
+$(eval $(call template,edgetypes, edgetypes ))
+
+#delete
+$(eval $(call template,delete, delete delete_input delete_output delete_port delete_cell delete_wire delete_proc ))
+$(eval $(call template,delete_mem, delete_mem ))
+
+#cover
+$(eval $(call template,cover, cover cover_q cover_o cover_dir cover_a ))
+
+.PHONY: all clean

MISC/cover/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

MISC/delete/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

MISC/delete_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

MISC/edgetypes/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

MISC/ltp/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

MISC/qwp/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+//always @(posedge cin)
+//	A <= o;
+
+assign cout =  cin? y : x;
+
+//middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

MISC/rename/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

MISC/run.sh

+#!/bin/bash
+
+set -ex
+test -d $1
+test -f scripts/$2.ys
+
+rm -rf $1/work_$2
+mkdir $1/work_$2
+cd $1/work_$2
+
+yosys -ql yosys.log ../../scripts/$2.ys
+
+if grep 'Assert' result.log || grep 'failed in' result.log || grep 'fail' result.log || grep 'ERROR' result.log; then
+	echo fail > ${1}_${2}.status
+else
+	echo pass > ${1}_${2}.status
+fi
+
+touch .stamp

MISC/scatter/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

MISC/scc/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

MISC/scripts/cover.ys

+read_verilog ../top.v
+tee -o result.log cover

MISC/scripts/cover_a.ys

+read_verilog ../top.v
+tee -o result.log cover -a out.txt

MISC/scripts/cover_dir.ys

+read_verilog ../top.v
+tee -o result.log cover -d out_dir

MISC/scripts/cover_o.ys

+read_verilog ../top.v
+tee -o result.log cover -o out.txt

MISC/scripts/cover_q.ys

+read_verilog ../top.v
+tee -o result.log cover -q

MISC/scripts/delete.ys

+read_verilog ../top.v
+tee -o result.log delete middle

MISC/scripts/delete_cell.ys

+read_verilog ../top.v
+tee -o result.log delete top/$1

MISC/scripts/delete_input.ys

+read_verilog ../top.v
+tee -o result.log delete -input middle/x

MISC/scripts/delete_mem.ys

+read_verilog ../top.v
+tee -o result.log delete top/$7

MISC/scripts/delete_output.ys

+read_verilog ../top.v
+tee -o result.log delete -output middle/o

MISC/scripts/delete_port.ys

+read_verilog ../top.v
+tee -o result.log delete -port top/A

MISC/scripts/delete_proc.ys

+read_verilog ../top.v
+tee -o result.log delete top/$3

MISC/scripts/delete_wire.ys

+read_verilog ../top.v
+tee -o result.log delete top/o

MISC/scripts/edgetypes.ys

+read_verilog ../top.v
+tee -o result.log edgetypes

MISC/scripts/ltp.ys

+read_verilog ../top.v
+proc
+tee -o result.log ltp

MISC/scripts/ltp_noff.ys

+read_verilog ../top.v
+proc
+tee -o result.log ltp -noff

MISC/scripts/qwp.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp

MISC/scripts/qwp_alpha.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -alpha

MISC/scripts/qwp_dump.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -dump out.html

MISC/scripts/qwp_grid.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -grid 4

MISC/scripts/qwp_ltr.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -ltr

MISC/scripts/qwp_v.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -v

MISC/scripts/rename.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename middle mid_module

MISC/scripts/rename_enumerate.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename -enumerate

MISC/scripts/rename_enumerate_pat.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename -enumerate -pattern '_%_' top

MISC/scripts/rename_hide.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename -hide middle mid

MISC/scripts/rename_src.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename -src

MISC/scripts/rename_top.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log rename -top new_top

MISC/scripts/scatter.ys

+read_verilog ../top.v
+proc
+tee -o result.log scatter

MISC/scripts/scc.ys

+read_verilog ../top.v
+proc
+tee -o result.log scc top

MISC/scripts/scc_all_cell_types.ys

+read_verilog ../top.v
+tee -o result.log scc -all_cell_types top

MISC/scripts/scc_expect.ys

+read_verilog ../top.v
+tee -o result.log scc -expect 0 top

MISC/scripts/scc_max_depth.ys

+read_verilog ../top.v
+tee -o result.log scc -max_depth 2 top

MISC/scripts/scc_nofeedback.ys

+read_verilog ../top.v
+tee -o result.log scc -nofeedback top

MISC/scripts/scc_select.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log scc -select top

MISC/scripts/scc_set_attr.ys

+read_verilog ../top.v
+tee -o result.log scc -set_attr attr true top

MISC/scripts/show.ys

+read_verilog ../top.v
+proc
+tee -o result.log show -viewer dummy.sh top

MISC/scripts/show_color.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -color red $add top

MISC/scripts/show_colorattr.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -colorattr attr top

MISC/scripts/show_colors.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -colors red green blue top

MISC/scripts/show_enum.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -enum top

MISC/scripts/show_format.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -format dot top

MISC/scripts/show_label.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -label adder $add top

MISC/scripts/show_lib.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -lib ../top.v top

MISC/scripts/show_long.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -long top

MISC/scripts/show_notitle.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -notitle top

MISC/scripts/show_pause.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -pause top

MISC/scripts/show_prefix.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log show -viewer dummy.sh -prefix pr top

MISC/scripts/show_signed.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -signed top

MISC/scripts/show_stretch.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -stretch top

MISC/scripts/show_viewer.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh top

MISC/scripts/show_width.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -width top

MISC/scripts/stat.ys

+read_verilog ../top.v
+proc
+tee -o result.log stat

MISC/scripts/stat_liberty.ys

+read_verilog ../top.v
+tee -o result.log stat -liberty ../lib.lib

MISC/scripts/stat_top.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log stat -top top

MISC/scripts/stat_width.ys

+read_verilog ../top.v
+tee -o result.log stat -width

MISC/scripts/test_abcloop.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop

MISC/scripts/test_abcloop_n.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop -n 50

MISC/scripts/test_abcloop_s.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop -s 50

MISC/scripts/test_cell.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $add

MISC/scripts/test_cell_aigmap.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -aigmap $add

MISC/scripts/test_cell_alu.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $alu

MISC/scripts/test_cell_const.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -const $add

MISC/scripts/test_cell_div.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 $div $mod

MISC/scripts/test_cell_edges.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -edges $add

MISC/scripts/test_cell_f.ys

+read_verilog ../gold.v
+synth -top gold
+write_ilang ilang.ilang
+design -reset
+tee -o result.log test_cell -f ilang.ilang

MISC/scripts/test_cell_fa.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $fa

MISC/scripts/test_cell_lcu.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $lcu

MISC/scripts/test_cell_lut.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $lut

MISC/scripts/test_cell_macc.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 $macc

MISC/scripts/test_cell_map.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 -map ../simlib.v $add

MISC/scripts/test_cell_mux.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $mux

MISC/scripts/test_cell_muxdiv.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -muxdiv $add

MISC/scripts/test_cell_n.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 50 $add

MISC/scripts/test_cell_noeval.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -noeval $add

MISC/scripts/test_cell_nosat.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -nosat $add

MISC/scripts/test_cell_pmux.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $pmux

MISC/scripts/test_cell_s.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -s 50 $add

MISC/scripts/test_cell_script.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -script ../test_cell_scr.ys $add

MISC/scripts/test_cell_simlib.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -simlib $add

MISC/scripts/test_cell_sop.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $sop

MISC/scripts/test_cell_v.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -v $add

MISC/scripts/test_cell_vlog.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -vlog vlog.v $add

MISC/scripts/test_cell_w.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -w pref $add

MISC/scripts/torder.ys

+read_verilog ../top.v
+tee -o result.log torder

MISC/scripts/torder_noautostop.ys

+read_verilog ../top.v
+tee -o result.log torder -noautostop

MISC/scripts/torder_stop.ys

+read_verilog ../top.v
+tee -o result.log torder -stop $add A

MISC/scripts/trace.ys

+read_verilog ../top.v
+tee -o result.log trace synth -top top