Add tests for issues 449-527

regression/Makefile

@@ -213,5 +213,26 @@ $(eval $(call template,issue_00432,issue_00432))
 #issue_00444
 $(eval $(call template,issue_00444,issue_00444))
 
+#issue_00449
+$(eval $(call template,issue_00449,issue_00449))
+
+#issue_00457
+$(eval $(call template,issue_00457,issue_00457))
+
+#issue_00474
+$(eval $(call template,issue_00474,issue_00474))
+
+#issue_00481
+$(eval $(call template,issue_00481,issue_00481))
+
+#issue_00502
+$(eval $(call template,issue_00502,issue_00502))
+
+#issue_00524
+$(eval $(call template,issue_00524,issue_00524))
+
+#issue_00527
+$(eval $(call template,issue_00527,issue_00527))
+
 
 .PHONY: all clean

regression/issue_00449/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+       // $dumpfile("testbench.vcd");
+       // $dumpvars(0, testbench);
+
+        #0 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+	wire b;
+
+	top uut (clk,b);
+
+	assert_X b_test(.clk(clk), .A(b));
+
+endmodule

regression/issue_00449/top.v

+module top(i_clk,b);
+input i_clk;
+output b;
+
+wire value = 0;
+
+
+reg f_past_gbl_clock_valid;
+initial f_past_gbl_clock_valid = 0;
+always @(posedge i_clk)
+  f_past_gbl_clock_valid <= 1'b1;
+
+always @(posedge i_clk)
+  if ((f_past_gbl_clock_valid)&&(!$rose(i_clk)))
+  begin
+     assert($stable(value));
+  end
+
+assign b = f_past_gbl_clock_valid;
+
+endmodule

regression/issue_00457/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+       // $dumpfile("testbench.vcd");
+       // $dumpvars(0, testbench);
+
+        #0 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+	wire b;
+
+	top uut (clk,b);
+
+	assert_X b_test(.clk(clk), .A(b));
+
+endmodule

regression/issue_00457/top.v

+module top(i_clk,b);
+input i_clk;
+output b;
+
+wire value = 0;
+
+
+reg f_past_gbl_clock_valid;
+initial f_past_gbl_clock_valid = 0;
+always @(posedge i_clk)
+  f_past_gbl_clock_valid <= 1'b1;
+
+function automatic [19:0] zz_coreArea_uartBridge_uartConfigReg_clockDivider(input dummy);
+    begin
+      zz_coreArea_uartBridge_uartConfigReg_clockDivider = (20'b00000000000000000000);
+      zz_coreArea_uartBridge_uartConfigReg_clockDivider = (20'b00000000000000011010);
+    end
+  endfunction
+
+assign b = f_past_gbl_clock_valid;
+
+endmodule

regression/issue_00474/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+       // $dumpfile("testbench.vcd");
+       // $dumpvars(0, testbench);
+
+        #0 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+	wire b;
+
+	top uut (clk,b);
+
+	assert_X b_test(.clk(clk), .A(b));
+
+endmodule

regression/issue_00474/top.v

+module top(i_clk,b);
+input i_clk;
+output b;
+
+reg f_past_gbl_clock_valid;
+initial f_past_gbl_clock_valid = 0;
+always @(posedge i_clk)
+  f_past_gbl_clock_valid <= 1'b1;
+assign b = f_past_gbl_clock_valid;
+
+endmodule

regression/issue_00481/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+       // $dumpfile("testbench.vcd");
+       // $dumpvars(0, testbench);
+
+        #0 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+	wire b;
+
+	top uut (clk,b);
+
+	assert_X b_test(.clk(clk), .A(b));
+
+endmodule

regression/issue_00481/top.v

+module top (
+		 input clkIn,
+		 output clkOut
+		 );
+
+
+ // Set up clock for 48Mhz with input of 12MHz
+   SB_PLL40_CORE #(
+		   .FEEDBACK_PATH("SIMPLE"),
+		   .PLLOUT_SELECT("GENCLK"),
+		   .DIVR(4'b0000),
+		   .DIVF(7'b0111111),
+		   .DIVQ(3'b100),
+		   .FILTER_RANGE(3'b001)
+		   ) uut (
+			  .LOCK(lock),
+			  .RESETB(1'b1),
+			  .BYPASS(1'b0),
+			  .REFERENCECLK(clkIn),
+			  .PLLOUTCORE(clkOut)
+			  );
+endmodule

regression/issue_00502/top.v

+module top (A, B, C, Y);
+    input    A, B, C;
+    output   Y;
+
+   MY_AND3 inst_t1 (.A(A), .B(B), .C(C), .Y(Y) );
+
+endmodule
+
+module MY_AND3 (A, B, C, Y);
+    input    A, B, C;
+    output   Y;
+
+//   MY_AND2 inst_a1 (.A(A), .B(B), .Y(\\SUM/N10) ); // will not read
+   MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name
+   MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) );
+
+endmodule
+
+module MY_AND2 (A, B, Y);
+    input     A, B;
+    output    Y;
+
+assign Y = A & B;
+
+endmodule

regression/issue_00524/top.v

+module top(
+    inout  a,
+    inout  b,
+    input  dir,
+);
+
+    wire aout, bout;
+    GP_IOBUF iobufa(
+        .IO(a),
+        .OUT(aout),
+        .IN(bout),
+        .OE(dir)
+    );
+    GP_IOBUF iobufb(
+        .IO(b),
+        .OUT(bout),
+        .IN(aout),
+        .OE(!dir)
+    );
+
+endmodule

regression/issue_00527/sd_rrmux.v

+//----------------------------------------------------------------------
+// Srdy/drdy round-robin arbiter
+// but without the one cycle decision delay.
+//
+// This component supports multiple round-robin modes:
+//
+// Mode 0 : Each input gets a single cycle, regardless of data
+//          availability.  This mode functions like a TDM
+//          demultiplexer.  Output flow control will cause the
+//          component to stall, so that inputs do not miss their
+//          turn due to flow control.
+// Mode 0 fast arb : Each input gets a single grant. If the
+//          output is not ready (p_drdy deasserted), then the
+//          machine will hold on that particular input until it
+//          receives a grant.  Once a single token has been
+//          accepted the machine will round-robin arbitrate.
+//          When there are no requests the machine returns to
+//          its default state.
+// Mode 1 : Each input can transmit for as long as it has data.
+//          When input deasserts, device will begin to hunt for a
+//          new input with data.
+// Mode 2 : Continue to accept input until the incoming data
+//          matches a particular "end pattern".  The end pattern
+//          is provided on the c_rearb (re-arbitrate) input.  When
+//          c_rearb is high, will hunt for new inputs on next clock.
+//
+// This component also supports two arbitration modes: slow and fast.
+// slow rotates the grant from requestor to requestor cycle by cycle,
+// so each requestor gets serviced at most once every #inputs cycles.
+// This can be useful for producing a TDM-type interface, however
+// requestors may be delayed waiting for the grant to come around even
+// if there are no other requestors.
+//
+// Fast mode immediately grants the highest-priority requestor, however
+// it is drdy-noncompliant (drdy will not be asserted until srdy is
+// asserted).
+//
+// Naming convention: c = consumer, p = producer, i = internal interface
+//----------------------------------------------------------------------
+//  Author: Frank Wang
+//
+// This block is uncopyrighted and released into the public domain.
+//----------------------------------------------------------------------
+`ifndef _SD_RRMUX_V_
+`define _SD_RRMUX_V_
+// Clocking statement for synchronous blocks.  Default is for
+// posedge clocking and positive async reset
+`ifndef SDLIB_CLOCKING 
+ `define SDLIB_CLOCKING posedge clk or posedge reset
+`endif
+
+// delay unit for nonblocking assigns, default is to #1 
+`ifndef SDLIB_DELAY 
+ `define SDLIB_DELAY #1  
+`endif
+
+module sd_rrmux
+  #(parameter width=8,
+    parameter inputs=2,
+    parameter mode=0,
+    parameter fast_arb=1)
+  (
+   input               clk,
+   input               reset,
+  
+   input [(width*inputs)-1:0] c_data,
+   input [inputs-1:0]      c_srdy,
+   output  [inputs-1:0]    c_drdy,
+   input                   c_rearb,  // for use with mode 2 only
+
+   output reg [width-1:0]  p_data,
+   output [inputs-1:0]     p_grant,
+   output reg              p_srdy,
+   input                   p_drdy
+   );
+  // bmp for the c_srdy that has just been granted and accepted by p_drdy
+  reg [inputs-1:0]    just_granted;
+  //control path, transit only after p_drdy ("accepted" part).
+  reg [inputs-1:0]    to_be_granted; 
+  //for data path, regardless of p_drdy, help to remove combo loops
+  //rational being, when p_drdy==1'b0, it doesn't matter what p_data is.
+  reg [inputs-1:0]    to_tx_data; 
+
+  wire [width-1:0]     rr_mux_grid [0:inputs-1];
+  reg 		       rr_locked;
+  reg nxt_rr_locked;   // ri lint_check_waive NOT_DRIVEN
+  genvar               i;
+  integer              j;
+
+  assign c_drdy = to_be_granted & {inputs{p_drdy}};
+  assign p_grant = to_be_granted;
+
+  function [inputs-1:0] nxt_grant;
+    input [inputs-1:0] cur_grant;
+    input [inputs-1:0] cur_req;
+    input              cur_accept;
+    reg [inputs-1:0]   msk_req;
+    reg [inputs-1:0]   tmp_grant;
+    reg [inputs-1:0]   tmp_grant2;
+
+    begin
+// scenario: 
+// in cycle 0, src 1 is granted and accepted by p_drdy,
+// in cycle 1, src 3 is requesting, but p_drdy is 0, so c_data3 is presented at p_data with p_srdy
+// in cycle 2, if src 2 comes in requesting, should hold src 3 at p_data till p_drdy, 
+//             src 2 will only participate in next round arb.
+// the way is in this scenario, pretend src2 is the just_granted in cycle 1.
+// so arbitration is excercies in two cases: (1): p_drdy, 
+// or (2) p_not_drdy, the immediate next c_not_srdy, but at least one remote c_srdy
+      
+      msk_req = cur_req & ~((cur_grant - 1) | cur_grant);
+      tmp_grant = msk_req & (~msk_req + 1);
+      tmp_grant2 = cur_req & (~cur_req + 1);
+
+      if(cur_accept)begin
+          if (msk_req != 0) nxt_grant = tmp_grant;
+          else nxt_grant = tmp_grant2;
+      //end else if (rem_neighbor_rearb) begin
+      end else if (| cur_req) begin
+          if (msk_req != 0) nxt_grant = {tmp_grant[0],tmp_grant[inputs-1:1]};
+          else nxt_grant = {tmp_grant2[0],tmp_grant2[inputs-1:1]};
+      end else begin
+          nxt_grant = cur_grant;
+      end
+    end
+  endfunction
+  
+  generate
+    for (i=0; i<inputs; i=i+1)
+      begin : grid_assign
+        //assign rr_mux_grid[i] = c_data >> (i*width);
+        assign rr_mux_grid[i] = c_data[i*width+width-1 : i*width]; 
+      end
+
+    if (mode == 2)
+      begin : tp_gen
+        always @*
+          begin
+            nxt_rr_locked = rr_locked;
+
+            if ((c_srdy & just_granted) & (!rr_locked))
+              nxt_rr_locked = 1;
+            else if ((c_srdy & just_granted & c_rearb))
+              nxt_rr_locked = 0;
+          end
+
+        always @(`SDLIB_CLOCKING)
+          begin
+            if (reset)
+              rr_locked <= 0;
+            else
+              rr_locked <= nxt_rr_locked;
+          end
+      end // block: tp_gen
+  endgenerate
+
+//  always @*
+//    begin
+//      p_data = 0;
+//      p_srdy = 0;
+//      for (j=0; j<inputs; j=j+1)
+//        if (just_granted[j])
+//          begin
+//            p_data = rr_mux_grid[j];
+//            p_srdy = c_srdy[j];
+//          end
+//    end
+always @(*) begin
+    p_srdy = | c_srdy;
+
+    p_data = {width{1'b0}};
+    for (j=0; j<inputs; j=j+1) begin
+        if (to_tx_data[j]) begin
+            p_data = rr_mux_grid[j];
+            p_srdy = c_srdy[j];
+        end
+    end
+end
+  
+  always @*
+    begin
+      to_tx_data = just_granted;
+      to_be_granted = just_granted;
+      if ((mode ==  1) & (|(c_srdy & just_granted)))
+        to_be_granted = just_granted;
+      else if ((mode == 0) && !fast_arb)begin
+        to_be_granted=p_drdy?{just_granted[0],just_granted[inputs-1:1]}:just_granted;
+        to_tx_data={just_granted[0],just_granted[inputs-1:1]};
+      end
+      //else if ((mode == 0) && |(just_granted & c_srdy) && !p_drdy && fast_arb)
+      //  to_be_granted = just_granted;
+      else if ((mode == 2) & (nxt_rr_locked | (|(c_srdy & just_granted))))
+        to_be_granted = just_granted;
+      else if (fast_arb) begin
+        to_be_granted=nxt_grant (just_granted, c_srdy, p_drdy);
+        to_tx_data = nxt_grant(just_granted, c_srdy, 1'b1);
+      end
+      else begin
+        to_be_granted=p_drdy?{just_granted[0],just_granted[inputs-1:1]}:just_granted;
+        to_tx_data={just_granted[0],just_granted[inputs-1:1]};
+      end
+    end
+
+  always @(`SDLIB_CLOCKING)
+    begin
+      if (reset)
+        just_granted <= {1'b1,{inputs-1{1'b0}}};
+      else
+        if (to_be_granted==0)
+            just_granted <= just_granted;
+        else
+            just_granted <= to_be_granted;
+    end
+
+endmodule 
+`endif //  _SD_RRMUX_V_

regression/issue_00527/syn.tcl

+# Basic synthesis file to replicate DFFSR bug
+
+yosys -import
+set libfile osu018_stdcells_edit.lib
+
+read_verilog -sv sd_rrmux.v
+
+# Vanilla synth flow
+hierarchy
+procs
+fsm
+opt
+techmap
+opt
+
+dfflibmap -liberty $libfile
+
+abc -liberty $libfile
+
+clean
+
+write_verilog sd_rrmux_osu.gv
+

regression/issue_00527/testcase

+#!/bin/bash
+
+yosys -t syn.tcl
+
+if grep -q DFFSR sd_rrmux_osu.gv; then
+  echo "FAILED -- DFFSR present in netlist"
+else
+  echo "PASSED -- DFFSR not present"
+fi
+

regression/run.sh

@@ -35,6 +35,38 @@ if [ "$1" = "issue_00089" ] ||\
 		fi
 	fi
 
+# cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
+elif [ "$1" = "issue_00502" ] ||\
+     [ "$1" = "issue_00524" ] ||\
+     [ "$1" = "issue_00527" ]; then
+
+	expected_string=""
+	expected="1"
+	if [ "$1" = "issue_00502" ]; then
+		expected_string="\\SUM/N10"
+	elif [ "$1" = "issue_00524" ]; then
+		expected_string="GP_INV"
+	elif [ "$1" = "issue_00527" ]; then
+		expected_string="DFFSR"
+		expected="0"
+	fi
+
+	yosys -ql yosys.log ../../scripts/$2.ys;
+	if grep "$expected_string" result.log; then
+		if [ $expected = "1" ]; then
+			echo pass > ${1}_${2}.status
+		else
+			echo fail > ${1}_${2}.status
+		fi
+	else
+		if [ $expected = "1" ]; then
+			echo fail > ${1}_${2}.status
+		else
+			echo pass > ${1}_${2}.status
+		fi
+	fi
+
+
 # cases with simulation checks
 else
 
@@ -44,12 +76,13 @@ else
 		iverilog_adds="../../../../../techlibs/xilinx/brams_bb.v"
 	elif [ "$1" = "issue_00160" ] ||\
 		 [ "$1" = "issue_00182" ] ||\
-		 [ "$1" = "issue_00183" ]; then
+		 [ "$1" = "issue_00183" ] ||\
+		 [ "$1" = "issue_00481" ]; then
 		iverilog_adds="../../../../../techlibs/ice40/cells_sim.v"
 	fi
 
 	yosys -ql yosys.log ../../scripts/$2.ys
-	iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v $iverilog_adds
+	iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v $iverilog_adds
 	if ! vvp -N testbench > testbench.log 2>&1; then
 		grep 'ERROR' testbench.log
 		echo fail > ${1}_${2}.status

regression/scripts/issue_00449.ys

+read_verilog -formal ../top.v
+synth -top top
+write_verilog synth.v

regression/scripts/issue_00457.ys

+read_verilog -formal ../top.v
+synth -top top
+write_verilog synth.v

regression/scripts/issue_00474.ys

+read_verilog -formal ../top.v
+verilog_defaults -push
+verilog_defaults -pop
+synth -top top
+write_verilog synth.v

regression/scripts/issue_00481.ys

+read_verilog ../top.v
+synth_ice40 -blif tlt.blif -top top
+write_verilog synth.v
+

regression/scripts/issue_00502.ys

+read_verilog ../top.v
+select n:\\SUM/N10
+tee -o result.log select -list
+

regression/scripts/issue_00524.ys

+read_verilog ../top.v
+synth_greenpak4 -part SLG46621V
+select GP_INV
+tee -o result.log select -list
+

regression/scripts/issue_00527.ys

+# Basic synthesis file to replicate DFFSR bug
+
+#yosys -import
+#set libfile osu018_stdcells_edit.lib
+
+read_verilog -sv ../sd_rrmux.v
+
+# Vanilla synth flow
+hierarchy
+proc
+fsm
+opt
+techmap
+opt
+
+dfflibmap -liberty ../osu018_stdcells_edit.lib
+
+abc -liberty ../osu018_stdcells_edit.lib
+
+clean
+
+select DFFSR
+tee -o result.log select -list
+