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- 28 Feb, 2019 7 commits
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- 21 Feb, 2019 4 commits
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Miodrag Milanovic committed
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Add missing scripts to misc/scripts
Miodrag Milanović committed -
SergeyDegtyar committed
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Add new tests to 'simple' and 'misc' test groups
Miodrag Milanović committed
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- 20 Feb, 2019 1 commit
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simple & misc =========== Note that some of commands you can not test with checking with testbench so those place in misc. 1. passes/cmds/add.cc Note that here you need to load some existing verilog and add additional wires, inputs or outputs 2. passes/cmds/blackbox.cc you could create design with sub module, execute blackbox and check if sub module is replaced with blackbox module. 3. passes/cmds/bugpoint.cc 4. passes/cmds/chformal.cc 5. passes/cmds/chtype.cc 6. passes/cmds/connect.cc Maybe can be covered together with add command 7.passes/cmds/connwrappers.cc 8. passes/cmds/design.cc missing covering -import option 9.passes/cmds/plugin.cc 10. passes/cmds/rename.cc rename parts of existing design 11. /passes/cmds/select.cc Lot of options is not used , so room to improve 12.passes/cmds/setattr.cc note there are 3 commands to cover here 13. passes/cmds/setundef.cc setting with one, anyseq, anyconst ... 14. passes/sat/assertpmux.cc 15. passes/sat/async2sync.cc 16. passes/sat/eval.cc 17. passes/sat/freduce.cc 18. passes/sat/miter.cc run with -assert option 19. passes/sat/sat.cc many options are not tested 20. passes/sat/sim.cc 21. passes/techmap/flowmap.cc
SergeyDegtyar committed
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- 11 Feb, 2019 1 commit
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Add new tests to 'simple' and 'misc' groups; Add test group for equiv_* commands.
Miodrag Milanović committed
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- 06 Feb, 2019 1 commit
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Testing problems: 1. coverage_html/passes/equiv/equiv_make.cc.gcov.html - 164-227 are not covered; 2. coverage_html/passes/equiv/equiv_add.cc.gcov.html - is not covered ("ERROR: This command must be executed in module context!")
SergeyDegtyar committed
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- 05 Feb, 2019 1 commit
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backends ======= 1. backends/firrtl/firrtl.cc – skipped because of error: ERROR: Unclocked write port 0 on memory top.ram. Add model with memory block too, so you can cover line block starting at line 419 simple ========= + 1. passes/techmap/attrmap.cc There is example in help block create example with (* keep="true" *) attribute and run example + 2. passes/techmap/dff2dffe.cc execute with -unmap parameter + 3. passes/techmap/dff2dffs.cc + 4. passes/techmap/extract.cc Lot of variations of input parameters is not excersised ? 5. passes/techmap/extract_counter.cc This is specific to greenpak4 architecture, but idea is to have counter in design and call this after synth_greenpak + 6. passes/techmap/shregmap.cc. This also seams to be greenpak4 specific, but extracting shift register misc ======== 1. passes/techmap/insbuf.cc Testing problems: 1. backends/firrtl/firrtl.cc – skipped because of error: ERROR: Unclocked write port 0 on memory top.ram. Add model with memory block too, so you can cover line block starting at line 419 2.dff2dffe -direct - skipped: ERROR: Found error in internal cell \dffe.$procdff$47 ($dffe) at 3.insbuf -buf $_BUF_ in out - skipped: ERROR: Found error in internal cell
SergeyDegtyar committed
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- 29 Jan, 2019 3 commits
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Add tests for MISC task list; Add test for write_table command
Miodrag Milanović committed -
SergeyDegtyar committed
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MISC ===== Tasks in this group are just generating some output, so no traditional test bench could be made. Writing output from yosys and checking if result is expected is advised. 1.http://scratch.clifford.at/coverage_html/passes/tests/test_abcloop.cc.gcov.html This represents some internal tests for ABC loops 2. http://scratch.clifford.at/coverage_html/passes/tests/test_cell.cc.gcov.html note that you need to provide multiple tests in order to cover testing of all cell types. Also output should be checked if it contain "Fail" or "Error" in it 3. http://scratch.clifford.at/coverage_html/passes/cmds/torder.cc.gcov.html Use some verilog file, do proc and this should display you all cells in designed ordered. Require multiple different parameters to cover all. 4.http://scratch.clifford.at/coverage_html/passes/cmds/trace.cc.gcov.html loading verilog file and doing "trace proc" will create output with additional logs, not much to check from output to be honest 5. http://scratch.clifford.at/coverage_html/passes/cmds/write_file.cc.gcov.html just write to file and check if written output is fine 6. http://scratch.clifford.at/coverage_html/passes/cmds/stat.cc.gcov.html if you have liberty cell library files, try it with those specified. 7. http://scratch.clifford.at/coverage_html/passes/cmds/show.cc.gcov.html note that you would always need to set -viewer since you do not wish to call graphwiz. Need covering of various parameters on a reasonable complicated design to cover. 8. http://scratch.clifford.at/coverage_html/passes/cmds/scc.cc.gcov.html detection of logic loops, output needs to be tested in order to check if loop was detected on not. 9. http://scratch.clifford.at/coverage_html/passes/cmds/scatter.cc.gcov.html After doing synth on existing design, just run this step, can do opt_clean after and there should be lot of temporary and unused wires removed. 10. http://scratch.clifford.at/coverage_html/passes/cmds/rename.cc.gcov.html can load design and rename top modue, output should contain module with new name 11. http://scratch.clifford.at/coverage_html/passes/cmds/qwp.cc.gcov.html Use it on simple design since it takes a while on big ones. 12. http://scratch.clifford.at/coverage_html/passes/cmds/ltp.cc.gcov.html Check if returns expected value for your design 13. http://scratch.clifford.at/coverage_html/passes/cmds/edgetypes.cc.gcov.html it just outputs report, so not sure what would be valid to check, just execute for now. 14. http://scratch.clifford.at/coverage_html/passes/cmds/delete.cc.gcov.html load existing design and try removing inputs, outputs,... complete design 15. http://scratch.clifford.at/coverage_html/passes/cmds/cover.cc.gcov.html it just prints report, so nothing to check
SergeyDegtyar committed
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- 27 Jan, 2019 1 commit
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Miodrag Milanovic committed
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- 25 Jan, 2019 3 commits
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add tests for synth_anlogic and 'regression'; Megre commit: "Fix tests according to latest yosys and proper...
Miodrag Milanović committed -
Miodrag Milanović committed
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Merge commit "Fix tests according to latest yosys and proper gitignore files". Make the same changes for 'regression'.
SergeyDegtyar committed
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- 24 Jan, 2019 1 commit
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Miodrag Milanovic committed
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