Commit 9059c863 by Eddie Hung

More stable naming

parent fdaf7677
......@@ -5,5 +5,5 @@ clean -purge
write_verilog synth7.v
# Check that shift registers with resets are not inferred into SRLs
cd $paramod\shift_reg\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\shift_reg\depth=131\inferred=1\init=1\neg_clk=1\er_is_reset=1; select t:SRL* -assert-count 0
cd synth; cd pos_clk_no_enable_no_init_not_inferred_with_reset; select t:SRL* -assert-count 0
cd synth; cd neg_clk_no_enable_with_init_with_inferred_with_reset; select t:SRL* -assert-count 0
......@@ -5,4 +5,4 @@ clean -purge
write_verilog synth8.v
# Check that wide shift registers are not a problem
cd $paramod\shift_reg\width=131\depth=131; select t:FD* -assert-count 0
cd synth; cd pos_clk_no_enable_no_init_not_inferred_N_width; select t:FD* -assert-count 0
......@@ -5,4 +5,4 @@ clean -purge
write_verilog synth9.v
# Check that wide shift registers are not a problem
cd $paramod\shift_reg\width=131\depth=131\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0
cd synth; cd neg_clk_no_enable_with_init_with_inferred_N_width; select t:FD* -assert-count 0
......@@ -42,7 +42,7 @@ generate
(* keep *)
shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, /*l*/, z);
`elsif TEST10
for (i = 1; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
for (i = 1; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred_var_len
shift_reg #(.depth(i+1), .fixed_length(0)) sr(clk, a[i], 1'b1, l[$clog2(i+1)-1:0], z[i]);
end
assign z[0] = 'b0; // Suppress no driver warning
......
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