More tests for inferred SRLs with INIT

architecture/synth_xilinx_srl/testbench.v

@@ -18,8 +18,8 @@ module testbench;
 
     reg [`N-1:0] a;
     reg e;
-    wire [`N-1:0] y1, y2, y3, y4;
-    wire [`N-1:0] z1, z2, z3, z4;
+    wire [`N-1:0] y1, y2, y3, y4, y5, y6;
+    wire [`N-1:0] z1, z2, z3, z4, z5, z6;
 
     top rtl (
         .clk (clk ),
@@ -28,7 +28,9 @@ module testbench;
         .z1 (y1),
         .z2 (y2),
         .z3 (y3),
-        .z4 (y4)
+        .z4 (y4),
+        .z5 (y5),
+        .z6 (y6)
     );
 
     synth uut (
@@ -38,7 +40,9 @@ module testbench;
         .z1 (z1),
         .z2 (z2),
         .z3 (z3),
-        .z4 (z4)
+        .z4 (z4),
+        .z5 (z5),
+        .z6 (z6)
     );
 
     always @(negedge clk)
@@ -57,6 +61,10 @@ module testbench;
             assert_dff z3n_test(.clk(~clk), .test(z3[i]), .pat(y3[i]));
             assert_dff z4p_test(.clk(clk), .test(z4[i]), .pat(y4[i]));
             assert_dff z4n_test(.clk(~clk), .test(z4[i]), .pat(y4[i]));
+            assert_dff z5p_test(.clk(clk), .test(z5[i]), .pat(y5[i]));
+            assert_dff z5n_test(.clk(~clk), .test(z5[i]), .pat(y5[i]));
+            assert_dff z6p_test(.clk(clk), .test(z6[i]), .pat(y6[i]));
+            assert_dff z6n_test(.clk(~clk), .test(z6[i]), .pat(y6[i]));
         end
     endgenerate
 

architecture/synth_xilinx_srl/top.v

 `include "defines.vh"
 
 module template(input clk, input a, input e, output z);
-parameter icell = 1;
+parameter inferred = 0;
 parameter init = 0;
 parameter neg_clk = 0;
-parameter len = 0;
+parameter len = 1;
 generate 
-    if (icell == 1) begin
+    if (inferred == 0) begin
         wire [len:0] int;
         assign int[0] = a;
         genvar i;
         for (i = 0; i < len; i=i+1) begin
-            if (neg_clk) begin
+            if (neg_clk)
                 \$_DFFE_NP_ r(.C(clk), .D(int[i]), .E(e), .Q(int[i+1]));
-                //if (init) initial r.Q = ~(i % 2);
-            end
-            else begin
+            else
                 \$_DFFE_PP_ r(.C(clk), .D(int[i]), .E(e), .Q(int[i+1]));
-                //if (init) initial r.Q = ~(i % 2);
-            end
         end
         assign z = int[len];
     end
     else begin
+        reg [len-1:0] int;
+
+        if (init) begin
+            genvar i;
+            for (i = 0; i < len; i=i+1)
+                initial int[i] = ~(i % 2);
+        end
+
+        if (len == 1) begin
+            if (neg_clk) begin
+                always @(negedge clk) if (e) int <= a;
+            end
+            else begin
+                always @(posedge clk) if (e) int <= a;
+            end
+            assign z = int;
+        end
+        else begin
+            if (neg_clk) begin
+                always @(negedge clk) if (e) int <= { int[len-2:0], a };
+            end
+            else begin
+                always @(posedge clk) if (e) int <= { int[len-2:0], a };
+            end
+            assign z = int[len-1];
+        end
     end
 endgenerate
 endmodule
 
-module top(input clk, input [`N-1:0] a, input e, output [`N-1:0] z1, z2, z3, z4);
+module top(input clk, input [`N-1:0] a, input e, output [`N-1:0] z1, z2, z3, z4, z5, z6);
 generate 
     genvar i;
-    for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_icell
+    for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred
         template #(.len(i+1)) sr(clk, a[i], 1'b1, z1[i]);
     end
-    for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_icell
+    for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_not_inferred
         template #(.len(i+1)) sr(clk, a[i], e, z2[i]);
     end
-    //for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_with_init_icell
-    //    template #(.len(i+1), .init(1)) sr(clk, a[i], 1'b1, z2[i]);
-    //end
-    for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_icell
-        template #(.len(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, z3[i]);
+    for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_with_init_inferred
+        template #(.len(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, z3[i]);
+    end
+    for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_not_inferred
+        template #(.len(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, z4[i]);
+    end
+    for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_inferred
+        template #(.len(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, z5[i]);
+    end
+    for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
+        template #(.len(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, z6[i]);
     end
-    //for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_with_init_icell
-    //    template #(.len(i+1), .neg_clk(1), .init(1)) sr(clk, a[i], 1'b1, z4[i]);
-    //end
 endgenerate
 endmodule