More tests

architecture/scripts/synth_xilinx_srl.ys

 read_verilog -icells ../top.v
 synth_xilinx
+write_verilog synth.v
 cd $paramod\template\len=1;   select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
 cd $paramod\template\len=2;   select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
 cd $paramod\template\len=3;   select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
@@ -130,4 +131,3 @@ cd $paramod\template\len=127; select t:FD* -assert-count 0; select t:SRL16E -ass
 cd $paramod\template\len=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
 cd $paramod\template\len=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
 cd $paramod\template\len=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
-write_verilog synth.v 

architecture/synth_xilinx_srl/top.v

-module template(input clk, input a, output z);
+module template(input clk, input a, input e, output z);
 parameter icell = 1;
+parameter init = 0;
+parameter neg_clk = 0;
 parameter len = 0;
 generate 
     if (icell == 1) begin
         wire [len:0] int;
         assign int[0] = a;
         genvar i;
-        for (i = 0; i < len; i++)
-            \$_DFF_P_ r( .C(clk), .D(int[i]), .Q(int[i+1]));
+        for (i = 0; i < len; i++) begin
+            if (neg_clk) begin
+                $_DFFE_NP_ r(.C(clk), .D(int[i]), .E(e), .Q(int[i+1]));
+                if (init) initial r.Q = ~(i % 2);
+            end
+            else begin
+                $_DFFE_PP_ r(.C(clk), .D(int[i]), .E(e), .Q(int[i+1]));
+                if (init) initial r.Q = ~(i % 2);
+            end
+        end
         assign z = int[len];
     end
     else begin
@@ -16,10 +26,20 @@ endgenerate
 endmodule
 
 `define N 131
-module top(input clk, input [`N-1:0] a, output [`N-1:0] z);
+module top(input clk, input [`N-1:0] a, output [`N-1:0] z1, z2, z3, z4);
 generate 
-genvar i;
-for (i = 0; i < `N; i++)
-    template #(.len(i+1)) sr(clk, a[i], z[i]);
+    genvar i;
+    for (i = 0; i < `N; i++) begin : pos_clk_no_enable_no_init_icell
+        template #(.len(i+1)) sr(clk, a[i], 1'b1, z1[i]);
+    end
+    for (i = 0; i < `N; i++) begin : pos_clk_no_enable_with_init_icell
+        template #(.len(i+1), .init(1)) sr(clk, a[i], 1'b1, z2[i]);
+    end
+    for (i = 0; i < `N; i++) begin : neg_clk_no_enable_no_init_icell
+        template #(.len(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, z3[i]);
+    end
+    for (i = 0; i < `N; i++) begin : neg_clk_no_enable_with_init_icell
+        template #(.len(i+1), .neg_clk(1), .init(1)) sr(clk, a[i], 1'b1, z4[i]);
+    end
 endgenerate
 endmodule