Commit a718457b by Eddie Hung

Small optimisations

parent b99c53fe
read_verilog -icells ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth.v
cd $paramod\template\len=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\template\len=2; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
......
......@@ -8,7 +8,7 @@ module testbench;
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
repeat (`N*3) begin
#5 clk = 1;
#5 clk = 0;
end
......
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