Merge pull request #7 from SergeyDegtyar/master

Add tests for MISC task list; Add test for write_table command

Makefile

 
-SUBDIRS := architecture backends bigsim frontends regression simple
+SUBDIRS := architecture backends bigsim frontends misc regression simple
 
 ifeq ($(VERIFIC),1)
 export VERIFIC=1

backends/Makefile

@@ -24,7 +24,7 @@ $(eval $(call template,write_aiger,write_aiger write_aiger_ascii write_aiger_zin
 $(eval $(call template,write_blif,write_blif write_blif_top write_blif_buf write_blif_unbuf write_blif_true  write_blif_false  write_blif_undef  write_blif_noalias  write_blif_icells  write_blif_gates  write_blif_conn  write_blif_attr  write_blif_param  write_blif_cname  write_blif_iname  write_blif_iattr  write_blif_blackbox  write_blif_impltf))
 
 #write_btor
-$(eval $(call template,write_btor,write_btor write_btor write_btor_v write_btor_s))
+$(eval $(call template,write_btor,write_btor write_btor_v write_btor_s))
 $(eval $(call template,write_btor_logic,write_btor write_btor_v write_btor_s))
 $(eval $(call template,write_btor_mem,write_btor_mem write_btor_mem_v write_btor_mem_s))
 $(eval $(call template,write_btor_pmux,write_btor_pmux))
@@ -75,6 +75,9 @@ $(eval $(call template,write_smv_cmos4,write_smv_cmos4))
 #write_spice
 $(eval $(call template,write_spice,write_spice write_spice_top write_spice_big_endian write_spice_neg_i write_spice_pos_i write_spice_nc_prefix write_spice_inames ))
 
+#write_table
+$(eval $(call template,write_table,write_table ))
+
 
 
 .PHONY: all clean

backends/scripts/write_table.ys

+read_verilog ../top.v
+proc
+write_table tb.tb
+write_verilog synth.v

backends/write_table/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

backends/write_table/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

misc/.gitignore

+*/work_*/
+/.stamp

misc/Makefile

+all: work
+	touch .stamp
+
+clean::
+	rm -f .stamp
+
+define template
+$(foreach design,$(1),
+$(foreach script,$(2),
+work:: $(design)/work_$(script)/.stamp
+
+$(design)/work_$(script)/.stamp:
+	bash run.sh $(design) $(script)
+
+clean::
+	rm -rf $(design)/work_$(script)
+))
+endef
+
+#test_abcloop
+$(eval $(call template,test_abcloop,test_abcloop test_abcloop_n test_abcloop_s ))
+
+#test_cell
+#test_cell_map - takes a lot of time
+# test_cell_mux, test_cell_pmux - is not supported
+$(eval $(call template,test_cell,test_cell test_cell_aigmap test_cell_const test_cell_edges test_cell_f  test_cell_div test_cell_muxdiv test_cell_n test_cell_noeval test_cell_nosat test_cell_s test_cell_script test_cell_simlib test_cell_v test_cell_vlog test_cell_w test_cell_alu test_cell_sop test_cell_lut test_cell_macc test_cell_lcu test_cell_fa))
+
+#torder
+$(eval $(call template,torder,torder torder_stop torder_noautostop ))
+
+#trace
+$(eval $(call template,trace,trace ))
+
+#write_file
+$(eval $(call template,write_file,write_file write_file_a ))
+
+#stat
+$(eval $(call template,stat, stat stat_top stat_width stat_liberty ))
+
+#show
+# show_pause - skipped
+$(eval $(call template,show, show show_colorattr show_colors show_color show_enum show_format show_label show_lib show_long show_notitle show_prefix show_signed show_stretch show_viewer show_width))
+
+#scc
+$(eval $(call template,scc, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
+
+#scatter
+$(eval $(call template,scatter, scatter ))
+
+#rename
+$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat))
+
+#qwp
+#qwp_v - exception
+#+ yosys -ql yosys.log ../../scripts/qwp_v.ys
+#run.sh: line 11: 28262 Floating point exception(core dumped) yosys -ql yosys.log ../../scripts/$2.ys
+$(eval $(call template,qwp, qwp qwp_ltr qwp_grid qwp_dump qwp_alpha))
+
+#ltp
+$(eval $(call template,ltp, ltp ltp_noff ))
+
+#edgetypes
+$(eval $(call template,edgetypes, edgetypes ))
+
+#delete
+$(eval $(call template,delete, delete delete_input delete_output delete_port delete_cell delete_wire delete_proc ))
+$(eval $(call template,delete_mem, delete_mem ))
+
+#cover
+$(eval $(call template,cover, cover cover_q cover_o cover_dir cover_a ))
+
+.PHONY: all clean

misc/cover/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc/delete/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc/delete_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

misc/edgetypes/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc/ltp/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc/qwp/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+//always @(posedge cin)
+//	A <= o;
+
+assign cout =  cin? y : x;
+
+//middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc/rename/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc/run.sh

+#!/bin/bash
+
+set -ex
+test -d $1
+test -f scripts/$2.ys
+
+rm -rf $1/work_$2
+mkdir $1/work_$2
+cd $1/work_$2
+
+yosys -ql yosys.log ../../scripts/$2.ys
+
+if grep 'Assert' result.log || grep 'failed in' result.log || grep 'fail' result.log || grep 'ERROR' result.log; then
+	echo fail > ${1}_${2}.status
+else
+	echo pass > ${1}_${2}.status
+fi
+
+touch .stamp

misc/scatter/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc/scc/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc/scripts/cover.ys

+read_verilog ../top.v
+tee -o result.log cover

misc/scripts/cover_a.ys

+read_verilog ../top.v
+tee -o result.log cover -a out.txt

misc/scripts/cover_dir.ys

+read_verilog ../top.v
+tee -o result.log cover -d out_dir

misc/scripts/cover_o.ys

+read_verilog ../top.v
+tee -o result.log cover -o out.txt

misc/scripts/cover_q.ys

+read_verilog ../top.v
+tee -o result.log cover -q

misc/scripts/delete.ys

+read_verilog ../top.v
+tee -o result.log delete middle

misc/scripts/delete_cell.ys

+read_verilog ../top.v
+tee -o result.log delete top/$1

misc/scripts/delete_input.ys

+read_verilog ../top.v
+tee -o result.log delete -input middle/x

misc/scripts/delete_mem.ys

+read_verilog ../top.v
+tee -o result.log delete top/$7

misc/scripts/delete_output.ys

+read_verilog ../top.v
+tee -o result.log delete -output middle/o

misc/scripts/delete_port.ys

+read_verilog ../top.v
+tee -o result.log delete -port top/A

misc/scripts/delete_proc.ys

+read_verilog ../top.v
+tee -o result.log delete top/$3

misc/scripts/delete_wire.ys

+read_verilog ../top.v
+tee -o result.log delete top/o

misc/scripts/edgetypes.ys

+read_verilog ../top.v
+tee -o result.log edgetypes

misc/scripts/ltp.ys

+read_verilog ../top.v
+proc
+tee -o result.log ltp

misc/scripts/ltp_noff.ys

+read_verilog ../top.v
+proc
+tee -o result.log ltp -noff

misc/scripts/qwp.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp

misc/scripts/qwp_alpha.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -alpha

misc/scripts/qwp_dump.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -dump out.html

misc/scripts/qwp_grid.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -grid 4

misc/scripts/qwp_ltr.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -ltr

misc/scripts/qwp_v.ys

+read_verilog ../top.v
+proc
+tee -o result.log qwp -v

misc/scripts/rename.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename middle mid_module

misc/scripts/rename_enumerate.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename -enumerate

misc/scripts/rename_enumerate_pat.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename -enumerate -pattern '_%_' top

misc/scripts/rename_hide.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename -hide middle mid

misc/scripts/rename_src.ys

+read_verilog ../top.v
+proc
+tee -o result.log rename -src

misc/scripts/rename_top.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log rename -top new_top

misc/scripts/scatter.ys

+read_verilog ../top.v
+proc
+tee -o result.log scatter

misc/scripts/scc.ys

+read_verilog ../top.v
+proc
+tee -o result.log scc top

misc/scripts/scc_all_cell_types.ys

+read_verilog ../top.v
+tee -o result.log scc -all_cell_types top

misc/scripts/scc_expect.ys

+read_verilog ../top.v
+tee -o result.log scc -expect 0 top

misc/scripts/scc_max_depth.ys

+read_verilog ../top.v
+tee -o result.log scc -max_depth 2 top

misc/scripts/scc_nofeedback.ys

+read_verilog ../top.v
+tee -o result.log scc -nofeedback top

misc/scripts/scc_select.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log scc -select top

misc/scripts/scc_set_attr.ys

+read_verilog ../top.v
+tee -o result.log scc -set_attr attr true top

misc/scripts/show.ys

+read_verilog ../top.v
+proc
+tee -o result.log show -viewer dummy.sh top

misc/scripts/show_color.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -color red $add top

misc/scripts/show_colorattr.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -colorattr attr top

misc/scripts/show_colors.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -colors red green blue top

misc/scripts/show_enum.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -enum top

misc/scripts/show_format.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -format dot top

misc/scripts/show_label.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -label adder $add top

misc/scripts/show_lib.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -lib ../top.v top

misc/scripts/show_long.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -long top

misc/scripts/show_notitle.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -notitle top

misc/scripts/show_pause.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -pause top

misc/scripts/show_prefix.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log show -viewer dummy.sh -prefix pr top

misc/scripts/show_signed.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -signed top

misc/scripts/show_stretch.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -stretch top

misc/scripts/show_viewer.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh top

misc/scripts/show_width.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -width top

misc/scripts/stat.ys

+read_verilog ../top.v
+proc
+tee -o result.log stat

misc/scripts/stat_liberty.ys

+read_verilog ../top.v
+tee -o result.log stat -liberty ../lib.lib

misc/scripts/stat_top.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log stat -top top

misc/scripts/stat_width.ys

+read_verilog ../top.v
+tee -o result.log stat -width

misc/scripts/test_abcloop.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop

misc/scripts/test_abcloop_n.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop -n 50

misc/scripts/test_abcloop_s.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop -s 50

misc/scripts/test_cell.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $add

misc/scripts/test_cell_aigmap.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -aigmap $add

misc/scripts/test_cell_alu.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $alu

misc/scripts/test_cell_const.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -const $add

misc/scripts/test_cell_div.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 $div $mod

misc/scripts/test_cell_edges.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -edges $add

misc/scripts/test_cell_f.ys

+read_verilog ../gold.v
+synth -top gold
+write_ilang ilang.ilang
+design -reset
+tee -o result.log test_cell -f ilang.ilang

misc/scripts/test_cell_fa.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $fa

misc/scripts/test_cell_lcu.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $lcu

misc/scripts/test_cell_lut.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $lut

misc/scripts/test_cell_macc.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 $macc

misc/scripts/test_cell_map.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 -map ../simlib.v $add

misc/scripts/test_cell_mux.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $mux

misc/scripts/test_cell_muxdiv.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -muxdiv $add

misc/scripts/test_cell_n.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 50 $add

misc/scripts/test_cell_noeval.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -noeval $add

misc/scripts/test_cell_nosat.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -nosat $add

misc/scripts/test_cell_pmux.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $pmux

misc/scripts/test_cell_s.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -s 50 $add

misc/scripts/test_cell_script.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -script ../test_cell_scr.ys $add

misc/scripts/test_cell_simlib.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -simlib $add

misc/scripts/test_cell_sop.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $sop

misc/scripts/test_cell_v.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -v $add

misc/scripts/test_cell_vlog.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -vlog vlog.v $add