Commit fac45755 by Eddie Hung

Add new synth_xilinx_srl tests

parent 8d7699bf
......@@ -53,6 +53,7 @@ $(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf
#xilinx
$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr))
$(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
#greenpak4
$(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
......
module template(input clk, input a, output z);
parameter icell = 1;
parameter len = 0;
generate
if (icell == 1) begin
wire [len:0] int;
assign int[0] = a;
genvar i;
for (i = 0; i < len; i++)
\$_DFF_P_ r( .C(clk), .D(int[i]), .Q(int[i+1]));
assign z = int[len];
end
else begin
end
endgenerate
endmodule
`define N 131
module top(input clk, input [`N-1:0] a, output [`N-1:0] z);
generate
genvar i;
for (i = 0; i < `N; i++)
template #(.len(i+1)) sr(clk, a[i], z[i]);
endgenerate
endmodule
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