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yosys-tests
Commit 1dd4e48c by Eddie Hung
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Add more tests

parent be125ff4
Showing with 56 additions and 20 deletions
architecture/run.sh
......@@ -55,7 +55,7 @@ elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif [ "$1" = "synth_xilinx_srl" ]; then
iverilog -DTEST1 synth1.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
for i in {2..11}; do
for i in {2..13}; do
run
iverilog -DTEST$i synth$i.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
done
......
architecture/scripts/synth_xilinx_srl.ys
......@@ -19,3 +19,7 @@ design -reset
script ../test10.ys
design -reset
script ../test11.ys
design -reset
script ../test12.ys
design -reset
script ../test13.ys
architecture/synth_xilinx_srl/test13.ys 0 → 100644
read_verilog -icells -DTEST13 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth13.v
# Check that non chain users block SRLs
cd synth; cd sr_fixed_length_other_users; select t:SRL* -assert-count 0
cd synth; cd sr_var_length_other_users; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/top.v
......@@ -5,61 +5,76 @@ generate
genvar i;
`ifdef TEST1
for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred
shift_reg #(.depth(i+1)) sr(clk, a[i], 1'b1, /*l*/, z[i]);
shift_reg #(.depth(i+1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state0 */);
end
`elsif TEST2
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_not_inferred
shift_reg #(.depth(i+1)) sr(clk, a[i], e, /*l*/, z[i]);
shift_reg #(.depth(i+1)) sr(clk, a[i], e, /*l*/, z[i], /* state0 */);
end
`elsif TEST3
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_with_init_inferred
shift_reg #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i]);
shift_reg #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i], /* state0 */);
end
`elsif TEST4
for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_not_inferred
shift_reg #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, /*l*/, z[i]);
shift_reg #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state0 */);
end
`elsif TEST5
for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_inferred
shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, /*l*/, z[i]);
shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state0 */);
end
`elsif TEST6
for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i]);
shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i], /* state0 */);
end
`elsif TEST7
// Check that use of resets block shreg
(* keep *)
shift_reg #(.depth(`N), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[1], r, /*l*/, z[0]);
(* keep *)
shift_reg #(.depth(`N), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[2], r, /*l*/, FIXME /*z[1]*/);
assign z[`N-1:2] = 'b0; // Suppress no driver warning
shift_reg #(.depth(129), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[1], r, /*l*/, z[0], /* state0 */);
// FIXME: YosysHQ/yosys#873
shift_reg #(.depth(129), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[2], r, /*l*/, FIXME1 /*z[1]*/, /* state0 */);
shift_reg #(.depth(128), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset_var_len(clk, a[2], r, l, z[2], /* state0 */);
// FIXME: YosysHQ/yosys#873
shift_reg #(.depth(129), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset_var_len(clk, a[3], r, l, FIXME2 /*z[3]*/, /* state0 */);
assign z[`N-1:4] = 'b0; // Suppress no driver warning
`elsif TEST8
// Check multi-bit works
(* keep *)
shift_reg #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, /*l*/, z);
shift_reg #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, /*l*/, z, /* state0 */);
`elsif TEST9
(* keep *)
shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, /*l*/, z);
shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, /*l*/, z, /* state0 */);
`elsif TEST10
for (i = 1; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred_var_len
shift_reg #(.depth(i+1), .fixed_length(0)) sr(clk, a[i], 1'b1, l[$clog2(i+1)-1:0], z[i]);
// FIXME: YosysHQ/yosys#873
for (i = /*0*/1; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred_var_len
shift_reg #(.depth(i+1), .fixed_length(0)) sr(clk, a[i], 1'b1, l[$clog2(i+1)-1:0], z[i], /* state0 */);
end
assign z[0] = 'b0; // Suppress no driver warning
`elsif TEST11
for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred_var_len
// FIXME: YosysHQ/yosys#873
for (i = /*0*/1; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred_var_len
shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1), .fixed_length(0)) sr(clk, a[i], e, l[$clog2(i+1)-1:0], z[i], /* state0 */);
end
assign z[0] = 'b0; // Suppress no driver warning
`elsif TEST12
for (i = 0; i < `N; i=i+1) begin : lfsr
lfsr #(.len(i+3)) sr(clk, z[i]);
end
`elsif TEST13
// Check that non chain users (i.e. output port, in non flattened case) block SRLs
shift_reg #(.depth(128), .output_index(0)) sr_fixed_length_other_users(clk, a[0], r, /*l*/, z[0], /* state0 */);
shift_reg #(.depth(128), .neg_clk(1), .inferred(1), .init(1), .fixed_length(0), .output_index(0)) sr_var_length_other_users(clk, a[1], e, l[$clog2(128)-1:0], z[1], /* state0 */);
assign z[`N-1:2] = 'b0; // Suppress no driver warning
`endif
endgenerate
endmodule
module shift_reg #(parameter width=1, depth=1) (input clk, input [width-1:0] a, input er, input [$clog2(depth)-1:0] l, output [width-1:0] z);
module shift_reg #(parameter width=1, depth=1) (input clk, input [width-1:0] a, input er, input [$clog2(depth)-1:0] l, output [width-1:0] z, output [depth-1:0] state0);
parameter inferred = 0;
parameter init = 0;
parameter neg_clk = 0;
parameter er_is_reset = 0;
parameter fixed_length = depth;
parameter output_index = -1;
generate
if (inferred == 0) begin
wire [depth:0] int [width-1:0];
......@@ -89,6 +104,10 @@ generate
assign z[j] = w[l];
end
end
if (output_index >= 0)
assign state0 = int[output_index][depth:1];
else
assign state0 = {depth{1'b0}};
end
else begin
reg [depth-1:0] int [width-1:0];
......@@ -126,7 +145,7 @@ generate
always @(negedge clk) if (er) int[j] <= { int[j][depth-2:0], a[j] };
end
else begin
always @(negedge clk or posedge er) if (er) int[j] <= 'b0; else int[j] <= { int[j][depth-2:0], a[j] };
always @(negedge clk or posedge er) if (er) int[j] <= {width{1'b0}}; else int[j] <= { int[j][depth-2:0], a[j] };
end
end
else begin
......@@ -134,7 +153,7 @@ generate
always @(posedge clk) if (er) int[j] <= { int[j][depth-2:0], a[j] };
end
else begin
always @(posedge clk or posedge er) if (er) int[j] <= 'b0; else int[j] <= { int[j][depth-2:0], a[j] };
always @(posedge clk or posedge er) if (er) int[j] <= {width{1'b0}}; else int[j] <= { int[j][depth-2:0], a[j] };
end
end
if (fixed_length > 0)
......@@ -143,6 +162,10 @@ generate
assign z[j] = int[j][l];
end
end
if (output_index >= 0)
assign state0 = int[output_index];
else
assign state0 = {depth{1'b0}};
end
endgenerate
endmodule
......
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