Working

architecture/run.sh

@@ -68,8 +68,8 @@ elif [ "$1" = "synth_xilinx_srl" ]; then
     iverilog -DTEST8 synth8.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
     run
     iverilog -DTEST9 synth9.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    #run
-    #iverilog -DTEST10 synth10.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
+    run
+    iverilog -DTEST10 synth10.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
 elif [ "$1" = "synth_greenpak4" ]; then
     iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
 else 

architecture/synth_xilinx_srl/test7.ys

@@ -6,4 +6,4 @@ write_verilog synth7.v
 
 # Check that shift registers with resets are not inferred into SRLs
 cd $paramod\shift_reg\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
-cd $paramod\shift_reg\inferred=1\init=1\neg_clk=1\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
+cd $paramod\shift_reg\depth=131\inferred=1\init=1\neg_clk=1\er_is_reset=1; select t:SRL* -assert-count 0

architecture/synth_xilinx_srl/test9.ys

@@ -5,4 +5,4 @@ clean -purge
 write_verilog synth9.v
 
 # Check that wide shift registers are not a problem
-cd $paramod\shift_reg\width=131\inferred=1\init=1\neg_clk=1\depth=131; select t:FD* -assert-count 0
+cd $paramod\shift_reg\width=131\depth=131\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0

architecture/synth_xilinx_srl/testbench.v

@@ -18,6 +18,7 @@ module testbench;
 
     reg [`N-1:0] a;
     reg e, r;
+    reg [$clog2(`N)-1:0] l;
     wire [`N-1:0] y;
     wire [`N-1:0] z;
 
@@ -26,6 +27,7 @@ module testbench;
         .a (a),
         .e (e),
         .r (r),
+        .l (l),
         .z (y)
     );
 
@@ -34,12 +36,14 @@ module testbench;
         .a (a),
         .e (e),
         .r (r),
+        .l (l),
         .z (z)
     );
 
     always @(negedge clk) begin
         e <= $random;
         r <= $random;
+        l <= $random;
     end
 
     generate

architecture/synth_xilinx_srl/top.v

 `include "defines.vh"
 
-module top(input clk, input [`N-1:0] a, input e, r, output [`N-1:0] z);
+module top(input clk, input [`N-1:0] a, input e, r, input [$clog2(`N)-1:0] l, output [`N-1:0] z);
 generate 
     genvar i;
 `ifdef TEST1
     for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred
-        shift_reg #(.depth(i+1)) sr(clk, a[i], 1'b1, z[i]);
+        shift_reg #(.depth(i+1)) sr(clk, a[i], 1'b1, /*l*/, z[i]);
     end
 `elsif TEST2
     for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_not_inferred
-        shift_reg #(.depth(i+1)) sr(clk, a[i], e, z[i]);
+        shift_reg #(.depth(i+1)) sr(clk, a[i], e, /*l*/, z[i]);
     end
 `elsif TEST3
     for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_with_init_inferred
-        shift_reg #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, z[i]);
+        shift_reg #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i]);
     end
 `elsif TEST4
     for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_not_inferred
-        shift_reg #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, z[i]);
+        shift_reg #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, /*l*/, z[i]);
     end
 `elsif TEST5
     for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_inferred
-        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, z[i]);
+        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, /*l*/, z[i]);
     end
 `elsif TEST6
     for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
-        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, z[i]);
+        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i]);
     end
 `elsif TEST7
     // Check that use of resets block shreg
     (* keep *)
-    shift_reg #(.depth(`N), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[1], r, z[0]);
+    shift_reg #(.depth(`N), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[1], r, /*l*/, z[0]);
     (* keep *)
-    shift_reg #(.depth(`N), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[2], r, FIXME /*z[1]*/);
+    shift_reg #(.depth(`N), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[2], r, /*l*/, FIXME /*z[1]*/);
     assign z[`N-1:2] = 'b0; // Suppress no driver warning
 `elsif TEST8
     // Check multi-bit works
     (* keep *)
-    shift_reg #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, z);
+    shift_reg #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, /*l*/, z);
 `elsif TEST9
     (* keep *)
-    shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, z);
+    shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, /*l*/, z);
 `elsif TEST10
+    for (i = 1; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
+        shift_reg #(.depth(i+1), .fixed_length(0)) sr(clk, a[i], 1'b1, l[$clog2(i+1)-1:0], z[i]);
+    end
+    assign z[0] = 'b0; // Suppress no driver warning
 `endif
 endgenerate
 endmodule
 
-module shift_reg #(parameter width=1) (input clk, input [width-1:0] a, input er, output [width-1:0] z);
+module shift_reg #(parameter width=1, depth=1) (input clk, input [width-1:0] a, input er, input [$clog2(depth)-1:0] l, output [width-1:0] z);
 parameter inferred = 0;
 parameter init = 0;
 parameter neg_clk = 0;
-parameter depth = 1;
 parameter er_is_reset = 0;
+parameter fixed_length = depth;
 generate 
     if (inferred == 0) begin
         wire [depth:0] int [width-1:0];
 
         genvar j;
         for (j = 0; j < width; j=j+1) begin
+            wire [depth-1:0] w;
             assign int[j][0] = a[j];
             genvar i;
             for (i = 0; i < depth; i=i+1) begin
@@ -72,7 +77,13 @@ generate
                     else
                         \$_DFF_PP0_ r(.C(clk), .D(int[j][i]), .R(er), .Q(int[j][i+1]));
             end
-            assign z[j] = int[j][depth];
+            if (fixed_length > 0)
+                assign z[j] = int[j][fixed_length];
+            else begin
+                //assign z[j] = int[j][l+1];
+                assign w = int[j][depth:1];
+                assign z[j] = w[l];
+            end
         end
     end
     else begin
@@ -122,7 +133,10 @@ generate
                         always @(posedge clk or posedge er) if (er) int[j] <= 'b0; else int[j] <= { int[j][depth-2:0], a[j] };
                     end
                 end
-                assign z[j] = int[j][depth-1];
+                if (fixed_length > 0)
+                    assign z[j] = int[j][fixed_length-1];
+                else
+                    assign z[j] = int[j][l];
             end
         end
     end