Add new tests to backends and architecture;

Add new tests to backends and architecture;
Merge commit "Add regression test for Yosys PR 896"

Fix synth_greenpak4.ys script

Add new tests to simple,misc,architecture

Add new tests to simple and misc groups

Add regression test for Yosys PR 896

 Add new tests to 'simple' and 'misc' groups

Signed-off-by: David Shah <dave@ds0.me>

Testing problems:

1. "sat -tempinduct_def":
+#ERROR: Assert `!undef_mode || model_undef' failed in
./kernel/satgen.h:90.

2. "share -force":
+#ERROR: Abort in passes/opt/share.cc:724.

Add new tests for issues #567-865

issue_00865 - test failed (should be ok after merge
https://github.com/YosysHQ/yosys/pull/866)

[tests] Add -chparam option to verific command

Add tests for issues from 111 to 527 that I could automate.

Add new tests to 'regression' test group

'a'.

Add tests for splitnets command
Expand coverage for trace command
Expand coverage for splice command (tests for options)
Expand coverage for scc command (different loops)
Expand coverage for rename command
Change test for passes/techmap/deminout
Update test for 'dff2dffe -direct' command
Add test for 'dffsr2dff' command
Expand coverage for iopadmap command

testing problems:
Issue #61 does not contain enough info.
Issues #82 and #83 I skipped because of errors.

---------------------

All of tasks will go to group regression, please change naming
convention there so files are named according to issue number (for
example issue_86 for directory and issue_86.ys script)
directory should contain exact example from issue, or in case it was
just generally described you can create your own example according to
explanation.

Idea for these tasks is not getting greater coverage  but making sure
old issues fixed are never broken again. Usually problem was failing of
yosys to generate any kind of output, in most of cases bellow, so just
checking if yosys did not assert any error is enough at least for these.
Issues bellow are taken from last two pages on issue tracker. Some of
these can really be trivial, and issue contains all info you need. Some
maybe need more thinking to be sure that you understood issue correctly.
In any case you are free to continue going trough the list of issues and
select new from it to cover.
I will see to crate some online spreadsheet that will have issue number,
type (if it is something that needed to be fixed or was a new feature or
some user error, and will have a status if it is covered by test or not.
That way we can have better overview what is going on.
So if you see that something is without a way to reproduce, or it was
user error just skip it, and when we have a spreadsheet we can update
there.

1. https://github.com/YosysHQ/yosys/issues/86
2. https://github.com/YosysHQ/yosys/issues/85
3. https://github.com/YosysHQ/yosys/issues/84
4. https://github.com/YosysHQ/yosys/issues/83
5. https://github.com/YosysHQ/yosys/issues/82
6. https://github.com/YosysHQ/yosys/issues/81
7. https://github.com/YosysHQ/yosys/issues/78
8. https://github.com/YosysHQ/yosys/issues/71
9. https://github.com/YosysHQ/yosys/issues/67
10. https://github.com/YosysHQ/yosys/issues/65
11. https://github.com/YosysHQ/yosys/issues/61
12. https://github.com/YosysHQ/yosys/issues/59
13. https://github.com/YosysHQ/yosys/issues/41
14. https://github.com/YosysHQ/yosys/issues/18

Add missing scripts to misc/scripts

Add new tests to 'simple' and 'misc' test groups

simple & misc
===========
Note that some of commands you can not test with checking with testbench
so those place in misc.

1. passes/cmds/add.cc
Note that here you need to load some existing verilog and add additional
wires, inputs or outputs
2. passes/cmds/blackbox.cc
you could create design with sub module, execute blackbox  and check if
sub module is replaced with blackbox module.
3. passes/cmds/bugpoint.cc

4. passes/cmds/chformal.cc

5. passes/cmds/chtype.cc

6. passes/cmds/connect.cc
Maybe can be covered together with add command

7.passes/cmds/connwrappers.cc

8. passes/cmds/design.cc
missing covering -import option

9.passes/cmds/plugin.cc

10. passes/cmds/rename.cc
rename parts of existing design

11. /passes/cmds/select.cc
Lot of options is not used , so room to improve

12.passes/cmds/setattr.cc
note there are 3 commands to cover here

13. passes/cmds/setundef.cc
setting with one, anyseq, anyconst ...

14. passes/sat/assertpmux.cc
15. passes/sat/async2sync.cc
16. passes/sat/eval.cc
17. passes/sat/freduce.cc
18. passes/sat/miter.cc
run with -assert option
19. passes/sat/sat.cc
many options are not tested
20. passes/sat/sim.cc

21. passes/techmap/flowmap.cc

Add new tests to 'simple' and 'misc' groups;  Add test group for equiv_* commands.

Testing problems:

1. coverage_html/passes/equiv/equiv_make.cc.gcov.html - 164-227 are not
covered;
2. coverage_html/passes/equiv/equiv_add.cc.gcov.html - is not covered
("ERROR: This command must be executed in module context!")

backends
=======
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419

simple
=========
+ 1. passes/techmap/attrmap.cc
There is example in help block create example with
(* keep="true" *) attribute and run example

+ 2. passes/techmap/dff2dffe.cc
execute with  -unmap parameter

+ 3. passes/techmap/dff2dffs.cc

+ 4. passes/techmap/extract.cc
Lot of variations of input parameters is not excersised

? 5. passes/techmap/extract_counter.cc
This is specific to greenpak4 architecture, but idea is to have counter
in design and call this after synth_greenpak

+ 6. passes/techmap/shregmap.cc.
This also seams to be greenpak4 specific, but extracting shift register

misc
========
1. passes/techmap/insbuf.cc

Testing problems:
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419
2.dff2dffe -direct - skipped: ERROR: Found error in internal cell
\dffe.$procdff$47 ($dffe) at
3.insbuf -buf $_BUF_ in out - skipped: ERROR: Found error in internal
cell