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yosys-tests
Unverified Commit f76690a5 by Miodrag Milanović Committed by GitHub
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Merge pull request #11 from SergeyDegtyar/master 

Add new tests to 'regression' test group
parents 8d7699bf 92201d14
Showing with 1447 additions and 4 deletions
misc/Makefile
......@@ -30,6 +30,7 @@ $(eval $(call template,torder,torder torder_stop torder_noautostop ))
#trace
$(eval $(call template,trace,trace ))
$(eval $(call template,trace_mem,trace_mem ))
#write_file
$(eval $(call template,write_file,write_file write_file_a ))
......@@ -43,6 +44,9 @@ $(eval $(call template,show, show show_colorattr show_colors show_color show_enu
#scc
$(eval $(call template,scc, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
$(eval $(call template,scc_feedback, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
$(eval $(call template,scc_hier_feedback, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
#scatter
$(eval $(call template,scatter, scatter ))
......@@ -140,4 +144,11 @@ $(eval $(call template,sat, sat_dump_cnf sat_dump_json sat_dump_vcd sat_initstep
$(eval $(call template,sim,sim sim_a sim_clock sim_d sim_n sim_rstlen sim_vcd sim_w sim_zinit ))
$(eval $(call template,sim_mem,sim sim_a sim_clockn sim_clock_mem sim_d sim_n sim_resetn sim_reset sim_rstlen sim_vcd sim_w sim_zinit_mem ))
#splitnets
$(eval $(call template,splitnets, splitnets splitnets_format splitnets_ports splitnets_driver splitnets_dpf ))
$(eval $(call template,splitnets_logic, splitnets splitnets_format splitnets_ports splitnets_driver splitnets_dpf ))
#splice
$(eval $(call template,splice, splice splice_sel_by_cell splice_sel_by_wire splice_sel_any_bit splice_wires splice_no_outputs splice_port splice_no_port ))
.PHONY: all clean
misc/scc_feedback/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o_mid,o_rtl;
always @(posedge cin)
A <= o_mid;
assign o_mid = x & o_rtl;
assign o_rtl = y & o_mid;
endmodule
misc/scc_hier_feedback/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o_mid,o_rtl;
always @(posedge cin)
A <= o_mid;
middle u_mid (.x(x),.y(o_rtl),.o(o_mid));
u_rtl inst_u_rtl (.x(o_mid),.y(y),.o(o_rtl));
endmodule
module middle
(
input x,
input y,
output o
);
wire o1,o2;
assign o1 = x & o2;
assign o2 = y & o1;
assign o = o1;
endmodule
module u_rtl
(
input x,
input y,
output o
);
wire o1,o2;
assign o1 = x & o2;
assign o2 = y & o1;
assign o = o1;
endmodule
misc/scripts/rename_wire.ys
read_verilog ../top.v
proc
tee -o result.log rename -wire middle mid_module
tee -o result.log rename -wire o mid_o
misc/scripts/scc.ys
read_verilog ../top.v
proc
tee -o result.log scc top
synth
tee -o result.log scc top
misc/scripts/splice.ys 0 → 100644
read_verilog ../top.v
tee -o result.log splice
proc
tee -o result.log splice
synth
tee -o result.log splice
misc/scripts/splice_no_outputs.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -no_outputs
misc/scripts/splice_no_port.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -no_port q_b
misc/scripts/splice_port.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -port q_b
misc/scripts/splice_sel_any_bit.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -sel_any_bit
misc/scripts/splice_sel_by_cell.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -sel_by_cell
misc/scripts/splice_sel_by_wire.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -sel_by_wire
misc/scripts/splice_wires.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log splice -wires
misc/scripts/splitnets.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets
misc/scripts/splitnets_dpf.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets -driver -ports -format www
misc/scripts/splitnets_driver.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets -driver
misc/scripts/splitnets_format.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets -format ()
misc/scripts/splitnets_ports.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log splitnets -ports
misc/scripts/trace.ys
read_verilog ../top.v
tee -o result.log trace synth -top top
proc
tee -o result.log trace synth -top top
synth
tee -o result.log trace synth -top top
misc/scripts/trace_mem.ys 0 → 100644
read_verilog ../top.v
tee -o result.log trace synth -top top
proc
memory
tee -o result.log trace synth -top top
synth
tee -o result.log trace synth -top top
misc/splice/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
misc/splitnets/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
misc/splitnets_logic/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/trace_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
regression/Makefile
......@@ -20,4 +20,99 @@ endef
#case_stmt_assertion
$(eval $(call template,case_stmt_assertion,case_stmt_assertion))
#issue_00018
$(eval $(call template,issue_00018,issue_00018))
#issue_00041
$(eval $(call template,issue_00041,issue_00041))
#issue_00059
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
$(eval $(call template,issue_00065,issue_00065))
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
#issue_00071
$(eval $(call template,issue_00071,issue_00071))
#issue_00078 What should be in top.v?
$(eval $(call template,issue_00078,issue_00078))
#issue_00081
$(eval $(call template,issue_00081,issue_00081))
#issue_00082
#yosys> read_verilog top_fault.v
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top_fault.v' to AST representation.
#top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
#
#$(eval $(call template,issue_00082,issue_00082))
#issue_00083
#Warning: Deep recursion in AST simplifier.
#Does this design contain insanely long expressions?
#run.sh: line 21: 17264 Segmentation fault (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
#make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
#
#$(eval $(call template,issue_00083,issue_00083))
#issue_00084
$(eval $(call template,issue_00084,issue_00084))
#issue_00085
$(eval $(call template,issue_00085,issue_00085))
#issue_00086
$(eval $(call template,issue_00086,issue_00086))
#issue_00088
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top.v' to AST representation.
#top.v:6: ERROR: syntax error, unexpected $undefined
#$(eval $(call template,issue_00089,issue_00089))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
# correct behavior
#../top.v:1: syntax error
#../top.v:1: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00093,issue_00093))
#issue_00095
#../top.v:1: syntax error
#../top.v:1: error: Invalid variable list in port declaration.
#../top.v:1: error: duplicate declaration for net or variable 'c' in 'a'.
#$(eval $(call template,issue_00095,issue_00095))
#issue_00096
#../top.v:2: syntax error
#../top.v:1: error: syntax error in integer variable list.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00096,issue_00096))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
#issue_00099
$(eval $(call template,issue_00099,issue_00099))
#issue_00102
$(eval $(call template,issue_00102,issue_00102))
#issue_00111
$(eval $(call template,issue_00111,issue_00111))
.PHONY: all clean
regression/issue_00018/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00018/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
regression/issue_00041/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00041/top.v 0 → 100644
module top(b);
input b;
task DoSomething(input [7:0] A);
endtask
endmodule
regression/issue_00059/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00059/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00065/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00065/top.v 0 → 100644
module top(
alu_data_d_in,
alu_data_d_out
);
input [7:0]alu_data_d_in;
output[7:0]alu_data_d_out;
wire [7:0]swap_out;
genvar i;
generate
for ( i = 7 ; ( i >= 4 ) ; i = ( i - 1 ) )
begin : swap_h
assign swap_out[i] = alu_data_d_in[( ( i - 4 ) )];
end
endgenerate
generate
//for ( i = 0 ; ( i <4 ) ; i = ( i + 1 ) ) //OK
for ( i = 3 ; ( i >=0 ) ; i = ( i - 1 ) ) //FAIL
begin : swap_l
assign swap_out[i] = alu_data_d_in[(i+4 )];
end
endgenerate
assign alu_data_d_out = swap_out;
endmodule
regression/issue_00067/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00067/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00067/top_fault.v 0 → 100644
module top(input en, output reg y);
always @*
y = en & !y;
endmodule
regression/issue_00071/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00071/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00071/top_fault.v 0 → 100644
module top(b);
input b;
reg [31:0] reg_32 = 32'bX;
endmodule
regression/issue_00078/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00078/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00078/top_fault.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00081/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00081/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00081/top_fault.v 0 → 100644
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
endmodule
module demo_002(y0, y1, y2, y3);
output [63:0] y0, y1, y2, y3;
assign y0 = 1'b_ >= (-1 * -1.17);
assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
assign y3 = 1 ? -1 : 'd0;
endmodule
regression/issue_00082/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00082/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00082/top_fault.v 0 → 100644
module a(b);
input b;
reg c;
task a(b);
endmodule
regression/issue_00083/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00083/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00083/top_fault.v 0 → 100644
module a(b);
input b;
reg c;parameter
signed b=b;
endmodule
regression/issue_00084/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [9:0] addr = 0;
reg ce = 0;
wire [7:0] q;
top uut (
.clk(clk),
.addr(addr),
.ce(ce),
.q(q)
);
always @(posedge clk) begin
addr <= addr + 1;
end
always @(posedge clk) begin
#3;
ce <= !ce;
end
uut_mem_checker q_test(.clk(clk), .en(ce), .A(q));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'b00000000)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00084/top.v 0 → 100644
module top (addr, ce, q, clk);
input clk;
input [9:0] addr;
input ce;
output reg [7:0] q;
reg [7:0] ram[1023:0];
always @(posedge clk)
begin
if (ce)
begin
q <= ram[addr];
end
end
endmodule
regression/issue_00085/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00085/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00085/top_fault.v 0 → 100644
module a;assign a = 0'sh0;
endmodule
regression/issue_00086/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00086/top.v 0 → 100644
module top(b);
input b;
endmodule
regression/issue_00086/top_fault.v 0 → 100644
module top(b);
input b;
reg N=0.0/0'H0;
endmodule
regression/issue_00088/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00088/top.v 0 → 100644
parameter X = 2;
module top(b);
input b;
parameter Y = 3;
endmodule
regression/issue_00089/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00089/top.v 0 → 100644
module top(A, clk, rst);
input clk, rst;
output A;
always @(posedge clk, posedge rst) begin
A <= '0';
end; // << like this
endmodule
regression/issue_00091/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00091/top.v 0 → 100644
module top(A, clk, rst);
input clk, rst;
output A;
parameter GPIO_COUNT = 16;
initial begin
if (GPIO_COUNT < 0 || GPIO_COUNT > 16) begin
$display("Parameter Error: GPIO_COUNT must be in range 0..16");
$finish;
end
end
endmodule
regression/issue_00093/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00093/top.v 0 → 100644
module top(b);inout b;reg c;assign+0-c=b;endmodule
regression/issue_00095/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00095/top.v 0 → 100644
module top(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule
regression/issue_00096/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00096/top.v 0 → 100644
module top(b);integer
inout b;reg c;assign&0=0;assign 0=0;always
i=0;always
if(8)b=_;always
if(8)b=M&0;endmodule
regression/issue_00098/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
always @(clk)
a <= a + 1;
top uut (
.a (a),
.z (z)
);
assert_Z check_output(clk,z[0]);
endmodule
regression/issue_00098/top.v 0 → 100644
module top(a,z);
input [7:0] a;
output [7:0] z;
parameter pos = 1;
assign z = ff(a);
function [7:0] ff;
parameter pos2 = pos + 1;
input [7:0] arg1;
begin
ff = arg1[pos2:0];
end
endfunction
endmodule
regression/issue_00099/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
wire o1,o2,o3;
always @(clk)
a <= a + 1;
top uut (
.in (a),
.out (z),
.out1 (o1),
.out2 (o2),
.out3 (o3)
);
assert_Z check_output1(clk,o1);
assert_Z check_output2(clk,o2);
assert_Z check_output3(clk,o3);
endmodule
regression/issue_00099/top.v 0 → 100644
module top(in, out, out1, out2, out3);
input [7:0] in;
output [7:0] out;
output out1;
output out2;
output out3;
parameter p = 23;
function [7:0] test1;
input [7:0] i;
parameter p = 42;
begin
test1 = i + p;
end
endfunction
function [7:0] test2;
input [7:0] i;
parameter p2 = p+42;
begin
test2 = i + p2;
end
endfunction
function [7:0] test3;
input [7:0] i;
begin
test3 = i + p;
end
endfunction
assign out1 = test1(in);
assign out2 = test2(in);
assign out3 = test3(in);
endmodule
regression/issue_00102/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [35:0] b;
top uut (
.a (clk),
.b (b)
);
assert_Z check_output1(clk,b[0]);
endmodule
regression/issue_00102/top.v 0 → 100644
module top (
a, b
);
input a;
output [35:0] b;
reg [35:0] G;
reg F;
reg H;
reg I;
reg J;
reg [5:0] K;
reg [9:0] L;
reg [9:0] M;
assign b = muxer(G, {L , H , F , M, J , I}, K, 24, 0);
function [35:0] muxer;
input [35:0] vector;
input [23:0] slice;
input [5:0] index;
input size;
integer size;
input offset;
integer offset;
integer i;
reg [35:0] muxed_value;
begin
muxed_value = vector;
for (i = 0; i < 24; i = i+1)
muxed_value[index * size + offset + i] = slice[i];
muxer = muxed_value;
end
endfunction
endmodule
regression/issue_00111/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [127:0] state,key = 0;
wire [127:0] out;
/*always @(posedge clk)
begin
state = state + 2300;
key = key + 2500;
end
top uut (
.state (state ),
.key (key ),
.out (out )
);*/
/*genvar index;
generate
for (index=0; index < 128; index=index+25)
begin: gen_code_label
assert_Z check_output(clk,out[index]);
end
endgenerate*/
assert_Z check_output(clk,out[0]);
endmodule
regression/run.sh
......@@ -12,12 +12,12 @@ mkdir $1/work_$2
cd $1/work_$2
if [ "$2" = "verify" ]; then
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
elif [ "$2" = "falsify" ]; then
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
else
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v)
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v) ../../../../../techlibs/xilinx/brams_bb.v
fi
if [ "$2" = "falsify" ]; then
......
regression/scripts/issue_00018.ys 0 → 100644
read_verilog ../top.v
synth -top top
select -assert-any w:*i
write_verilog synth.v
regression/scripts/issue_00041.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00059.ys 0 → 100644
read_verilog ../top.v
#Myname: added some comment with a colon
synth -top top
write_verilog synth.v
regression/scripts/issue_00065.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00067.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00071.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00078.ys 0 → 100644
read_verilog ../top.v
hierarchy
splitnets -ports
write_verilog synth.v
regression/scripts/issue_00081.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00082.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00083.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00084.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -top top
write_verilog synth.v
regression/scripts/issue_00085.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00086.ys 0 → 100644
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00088.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00089.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00091.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00093.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00095.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00096.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00098.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
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