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yosys-tests
Unverified Commit 5a43d62a by Miodrag Milanović Committed by GitHub
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Merge pull request #20 from SergeyDegtyar/master 

Add new tests to simple,misc,architecture
parents 9ba42f44 b2a89977
Showing with 1877 additions and 4 deletions
architecture/Makefile
......@@ -23,21 +23,27 @@ $(eval $(call template,synth_achronix,synth_achronix synth_achronix_top synth_ac
#anlogic
$(eval $(call template,synth_anlogic,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
$(eval $(call template,synth_anlogic_fulladder,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
$(eval $(call template,synth_anlogic_mem,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime anlogic_determine_init_eqn))
#coolrunner2
$(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
$(eval $(call template,synth_coolrunner2_fulladder,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
#easic
#$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
#ecp5
$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr))
$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
$(eval $(call template,synth_ecp5_wide_ffs,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
#gowin
$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime))
$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten ))
$(eval $(call template,synth_gowin_mem,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten ))
#ice40
$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr))
$(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr))
$(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr))
#intel
$(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_noiopads synth_intel_nobram synth_intel_max10 ))
......@@ -56,5 +62,6 @@ $(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_b
#greenpak4
$(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
$(eval $(call template,synth_greenpak4_wide_ffs,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
.PHONY: all clean
architecture/run.sh
......@@ -11,18 +11,30 @@ cd $1/work_$2
yosys -ql yosys.log ../../scripts/$2.ys
if [ "$1" = "synth_ecp5" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
elif [ "$1" = "synth_ecp5_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
elif [ "$1" = "synth_achronix" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/achronix/speedster22i/cells_sim.v
elif [ "$1" = "synth_anlogic" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v ../../../../../techlibs/anlogic/eagle_bb.v
elif [ "$1" = "synth_coolrunner2" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
elif [ "$1" = "synth_coolrunner2_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
elif [ "$1" = "synth_gowin" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/gowin/cells_sim.v
elif [ "$1" = "synth_gowin_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/gowin/cells_sim.v
elif [ "$1" = "synth_ice40" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
elif [ "$1" = "synth_intel" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/max10/cells_sim.v
elif [ "$1" = "synth_intel_a10gx" ]; then
......@@ -41,7 +53,9 @@ elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
else
elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
else
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
fi
......
architecture/scripts/anlogic_determine_init_eqn.ys 0 → 100644
read_verilog ../top.v
read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v
proc
flatten
tribuf -logic
deminout
synth -run coarse
memory_bram -rules +/anlogic/drams.txt
techmap -map +/anlogic/drams_map.v
anlogic_determine_init
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine
techmap -map +/techmap.v -map +/anlogic/arith_map.v
dffsr2dff
techmap -D NO_LUT -map +/anlogic/cells_map.v
dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit
opt_expr -mux_undef
simplemap
abc -lut 5
clean
techmap -map +/anlogic/cells_map.v
clean
anlogic_eqn
write_verilog synth.v
architecture/scripts/ecp5_ffinit.ys 0 → 100644
read_verilog ../top.v
read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v
proc
flatten
tribuf -logic
deminout
synth -run coarse
memory_bram -rules +/ecp5/bram.txt
techmap -map +/ecp5/brams_map.v
opt -fast -mux_undef -undriven -fine
techmap -map +/techmap.v -map +/ecp5/arith_map.v
abc -dff
opt -fast -mux_undef -undriven -fine
dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
techmap -D NO_LUT -map +/ecp5/cells_map.v
opt_expr -mux_undef
simplemap
ecp5_ffinit
write_verilog synth.v
architecture/scripts/synth_coolrunner2_mem.ys 0 → 100644
read_verilog ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/SimDTM.v
#
synth_coolrunner2
write_verilog synth.v
architecture/scripts/synth_gowin_nobram.ys 0 → 100644
read_verilog ../top.v
synth_gowin -nobram
write_verilog synth.v
architecture/scripts/synth_gowin_noflatten.ys 0 → 100644
read_verilog ../top.v
synth_gowin -noflatten
write_verilog synth.v
architecture/scripts/synth_greenpak4.ys
read_verilog ../top.v
greenpak4_dffinv
synth_greenpak4
write_verilog synth.v
write_verilog synth.v
architecture/synth_anlogic_mem/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [5:0] addr_a = 0;
reg we_a = 0;
wire [7:0] q_a;
reg mem_init = 0;
top uut (
.data_a(data_a),
.addr_a(addr_a),
.we_a(we_a),
.clk(clk),
.q_a(q_a)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
addr_a <= addr_a + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
architecture/synth_anlogic_mem/top.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
architecture/synth_coolrunner2_fulladder/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_coolrunner2_fulladder/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_ecp5_wide_ffs/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, negedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( !dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, posedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
endmodule
architecture/synth_ecp5_wide_ffs/top.v 0 → 100644
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b0110;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0100;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0100;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 4'b0000;
`endif
endmodule
module dffsr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b1010;
`else
q <= d;
`endif
else if ( !pre )
q <= 4'b0101;
else
q <= d;
endmodule
module dffs
( input [3:0] d, input clk, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk, negedge pre )
if ( !pre )
q <= 4'b1111;
else
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
module ndffnsnr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( negedge clk, posedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0010;
`else
q <= d;
`endif
else if ( pre )
q <= 4'b1101;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b,b1,b2,b3,b4
);
wire b5,b6;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
dffs u_dffs (
.clk (clk ),
.pre (pre),
.d (a ),
.q (b5 )
);
dffse u_dffse (
.clk (clk ),
.pre (pre),
.en (en),
.d (a ),
.q (b6 )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_gowin_mem/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [5:0] addr_a = 0;
reg we_a = 0;
wire [7:0] q_a;
reg mem_init = 0;
top uut (
data_a[0],
data_a[1],
data_a[2],
data_a[3],
data_a[4],
data_a[5],
data_a[6],
data_a[7],
addr_a[0],
addr_a[1],
addr_a[2],
addr_a[3],
addr_a[4],
addr_a[5],
we_a,
clk,
q_a[0],
q_a[1],
q_a[2],
q_a[3],
q_a[4],
q_a[5],
q_a[6],
q_a[7]
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
addr_a <= addr_a + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
architecture/synth_gowin_mem/top.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
architecture/synth_greenpak4_wide_ffs/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, negedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( !dinA[1] )
dff <= 1'b1;
else
dff <= ~dinA[0];
always @( negedge clk, negedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( negedge clk, negedge dinA[2] )
if ( !dinA[2] )
adff <= 1'b0;
else
adff <= ~dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( negedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(~dff));
assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
endmodule
architecture/synth_greenpak4_wide_ffs/top.v 0 → 100644
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b0110;
`else
q <= d;
`endif
else
q <= d;
endmodule
module gp_dff
( input d, input clk, clr, output reg q );
wire nq;
GP_DFF u_gp_dffr (d,clk,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffr
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFR u_gp_dffr (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffs
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFS u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffsi
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFSI u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_latchs
( input d, input clk, clr, output reg q );
wire nq;
GP_DLATCHS u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module adffn
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0100;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0100;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 4'b0000;
`endif
endmodule
module dffsr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b1010;
`else
q <= d;
`endif
else if ( !pre )
q <= 4'b0101;
else
q <= d;
endmodule
module dffs
( input [3:0] d, input clk, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk, negedge pre )
if ( !pre )
q <= 4'b1111;
else
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
module ndffnsnr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( negedge clk, posedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0010;
`else
q <= d;
`endif
else if ( pre )
q <= 4'b1101;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b,b1,b2,b3,b4
);
wire [3:0] b5,b6,b7,b8,bn,a_i;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (~a ),
.q (bn )
);
assign b = ~bn;
dffs u_dffs (
.clk (clk ),
.pre (pre),
.d (a ),
.q (b5 )
);
gp_dffr u_gp_dffr (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b7[0] )
);
gp_dff u_gp_dff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b8[0] )
);
gp_dffs u_gp_dffs (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b7[1] )
);
gp_dffsi u_gp_dffsi (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b7[2] )
);
gp_latchs u_gp_latchs (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b7[3] )
);
dffse u_dffse (
.clk (clk ),
.pre (pre),
.en (en),
.d (~a ),
.q (b6 )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (~clr),
.pre (~pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (~clk ),
.clr (~clr),
.d (~a ),
.q (b2 )
);
assign a_i[1:0] = a[1:0];
assign a_i[3:2] = ~a[3:2];
adffn u_adffn (
.clk (clk ),
.clr (~clr),
.d (a_i ),
.q (b3 )
);
dffe u_dffe (
.clk (~clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_ice40_mem/init.txt 0 → 100644
/*xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
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@
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architecture/synth_ice40_mem/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [5:0] addr_a = 0;
reg we_a = 0;
wire [7:0] q_a;
reg mem_init = 0;
top uut (
.data_a(data_a),
.addr_a(addr_a),
.we_a(we_a),
.clk(clk),
.q_a(q_a)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
addr_a <= addr_a + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
architecture/synth_ice40_mem/top.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a,
output reg [15:0] q_b,
output reg [15:0] q_c
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("init.txt")
) \ram.0.0.0 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
.RCLK(clk),
.RCLKE(1'h1),
.RDATA(q_b),
.RE(1'h1),
.WADDR({ 5'h00, addr_a }),
.WCLK(clk),
.WCLKE(we_a),
.WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
.WE(1'h1)
);
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("../init.txt")
) \ram.0.0.1 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
.RCLK(clk),
.RCLKE(1'h1),
.RDATA(q_c),
.RE(1'h1),
.WADDR({ 5'h00, addr_a }),
.WCLK(clk),
.WCLKE(we_a),
.WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
.WE(1'h1)
);
endmodule
architecture/synth_ice40_wide_ffs/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, negedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( !dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, posedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
endmodule
architecture/synth_ice40_wide_ffs/top.v 0 → 100644
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b0110;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0100;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0100;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 4'b0000;
`endif
endmodule
module dffsr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b1010;
`else
q <= d;
`endif
else if ( !pre )
q <= 4'b0101;
else
q <= d;
endmodule
module dffs
( input [3:0] d, input clk, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk, negedge pre )
if ( !pre )
q <= 4'b1111;
else
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
module ndffnsnr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( negedge clk, posedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0010;
`else
q <= d;
`endif
else if ( pre )
q <= 4'b1101;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b,b1,b2,b3,b4
);
wire b5,b6;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
dffs u_dffs (
.clk (clk ),
.pre (pre),
.d (a ),
.q (b5 )
);
dffse u_dffse (
.clk (clk ),
.pre (pre),
.en (en),
.d (a ),
.q (b6 )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
misc/Makefile
......@@ -179,5 +179,8 @@ $(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 a
$(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
$(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
#hilomap
$(eval $(call template,hilomap, hilomap hilomap_hicell hilomap_locell hilomap_singleton hilomap_hicell_singleton hilomap_locell_singleton hilomap_hicell_locell_singleton))
.PHONY: all clean
misc/hilomap/top.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, posedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b,b2
);
dffsr u_dffsr (
.clk (clk ),
`ifndef BUG
.clr (1'b0),
.pre (1'b1),
`else
.clr (1'b1),
.pre (1'b0),
`endif
.d (a ),
.q (b )
);
dffsr u2_dffsr (
.clk (clk ),
`ifndef BUG
.clr (1'b0),
.pre (1'b1),
`else
.clr (1'b1),
.pre (1'b0),
`endif
.d (a ),
.q (b2 )
);
endmodule
misc/scripts/hilomap.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log hilomap
misc/scripts/hilomap_hicell.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log hilomap -hicell VCC V
misc/scripts/hilomap_hicell_locell_singleton.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log hilomap -locell GND G -hicell VCC V -singleton
misc/scripts/hilomap_hicell_singleton.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log hilomap -hicell VCC V -singleton
misc/scripts/hilomap_locell.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log hilomap -locell GND G
misc/scripts/hilomap_locell_singleton.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log hilomap -locell GND G -singleton
misc/scripts/hilomap_singleton.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log hilomap -singleton
simple/Makefile
......@@ -190,5 +190,10 @@ $(eval $(call template,proc_arst_reduce, proc_arst proc_arst_global_rst proc_ar
$(eval $(call template, submod, submod submod_top submod_copy submod_name submod_no_proc submod_no_hier))
$(eval $(call template, submod_mem, submod submod_top submod_copy submod_name submod_no_proc submod_no_hier submod_mem))
#prep
$(eval $(call template, prep, prep prep_top prep_auto_top prep_flatten prep_ifx prep_memx prep_nomem prep_nordff prep_rdff prep_nokeepdc prep_run prep_run_begin))
#synth
$(eval $(call template, synth, synth synth_top synth_auto_top synth_encfile synth_run synth_run_full synth_flatten synth_lut synth_nofsm synth_noabc synth_noabc_lut synth_noalumacc synth_nordff synth_noshare))
.PHONY: all clean
simple/prep/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/prep/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/scripts/prep.ys 0 → 100644
read_verilog ../top.v
prep
synth -top top
write_verilog synth.v
simple/scripts/prep_auto_top.ys 0 → 100644
read_verilog ../top.v
prep -auto-top
synth -top top
write_verilog synth.v
simple/scripts/prep_flatten.ys 0 → 100644
read_verilog ../top.v
prep -flatten
synth -top top
write_verilog synth.v
simple/scripts/prep_ifx.ys 0 → 100644
read_verilog ../top.v
prep -ifx
synth -top top
write_verilog synth.v
simple/scripts/prep_memx.ys 0 → 100644
read_verilog ../top.v
prep -memx
synth -top top
write_verilog synth.v
simple/scripts/prep_nokeepdc.ys 0 → 100644
read_verilog ../top.v
prep -nokeepdc
synth -top top
write_verilog synth.v
simple/scripts/prep_nomem.ys 0 → 100644
read_verilog ../top.v
prep -nomem
synth -top top
write_verilog synth.v
simple/scripts/prep_nordff.ys 0 → 100644
read_verilog ../top.v
prep -nordff
synth -top top
write_verilog synth.v
simple/scripts/prep_rdff.ys 0 → 100644
read_verilog ../top.v
prep -rdff
synth -top top
write_verilog synth.v
simple/scripts/prep_run.ys 0 → 100644
read_verilog ../top.v
prep -run begin:check
synth -top top
write_verilog synth.v
simple/scripts/prep_run_begin.ys 0 → 100644
read_verilog ../top.v
prep -run begin
synth -top top
write_verilog synth.v
simple/scripts/prep_top.ys 0 → 100644
read_verilog ../top.v
prep -top top
synth -top top
write_verilog synth.v
simple/scripts/synth.ys 0 → 100644
read_verilog ../top.v
synth
write_verilog synth.v
simple/scripts/synth_auto_top.ys 0 → 100644
read_verilog ../top.v
synth -auto-top
write_verilog synth.v
simple/scripts/synth_encfile.ys 0 → 100644
read_verilog ../top.v
synth -encfile enc.file
write_verilog synth.v
simple/scripts/synth_flatten.ys 0 → 100644
read_verilog ../top.v
synth -flatten
write_verilog synth.v
simple/scripts/synth_lut.ys 0 → 100644
read_verilog ../top.v
synth -lut 5
write_verilog synth.v
simple/scripts/synth_noabc.ys 0 → 100644
read_verilog ../top.v
synth -noabc
write_verilog synth.v
simple/scripts/synth_noabc_lut.ys 0 → 100644
read_verilog ../top.v
synth -noabc -lut 3
write_verilog synth.v
simple/scripts/synth_noalumacc.ys 0 → 100644
read_verilog ../top.v
synth -noalumacc
write_verilog synth.v
simple/scripts/synth_nofsm.ys 0 → 100644
read_verilog ../top.v
synth -nofsm
write_verilog synth.v
simple/scripts/synth_nordff.ys 0 → 100644
read_verilog ../top.v
synth -nordff
write_verilog synth.v
simple/scripts/synth_noshare.ys 0 → 100644
read_verilog ../top.v
synth -noshare
write_verilog synth.v
simple/scripts/synth_run.ys 0 → 100644
read_verilog ../top.v
synth -run begin
write_verilog synth.v
simple/scripts/synth_run_full.ys 0 → 100644
read_verilog ../top.v
synth -run begin:check
write_verilog synth.v
simple/scripts/synth_top.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/synth/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/synth/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
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