1. 25 Jan, 2019 1 commit
  2. 24 Jan, 2019 1 commit
    • add tests for synth_anlogic and 'regression' · e0c895b0
      1. Add tests for synth_anlogic command
      Now this tests are commented because of:
      + iverilog -o testbench ../testbench.v synth.v ../../common.v
      ../../../../../techlibs/common/simcells.v
      ../../../../../techlibs/anlogic/cells_sim.v
      ../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to bind
      wire/reg/memory `A' in `testbench.uut._09_'
      ../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to
      elaborate r-value: (INIT)>>(A)
      2 error(s) during elaboration.
      
      2. Add 'regression' test
      SergeyDegtyar committed
  3. 23 Jan, 2019 1 commit
  4. 15 Jan, 2019 1 commit
  5. 02 Jan, 2019 7 commits
  6. 19 Dec, 2018 1 commit
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  19. 26 Feb, 2018 2 commits