Commit f252c11a by Clifford Wolf

Add more verific/opers test cases

Signed-off-by: Clifford Wolf <clifford@clifford.at>
parent c41333f8
TESTS := wide_mux sel_mux
TESTS := wide_mux sel_mux select wselect rednor
all: $(addsuffix .status,$(TESTS))
......
module top (input [6:0] a, output y);
assign y = ~|a;
endmodule
module top (input [2:0] s, input [7:0] a, output y);
module top (input [2:0] s, input [5:0] a, output y);
assign y = a[s];
endmodule
module top (input [5:0] s, input [6:0] a, output reg y);
always @* begin
(* parallel_case *)
casez (s)
6'b?????1: y = a[0];
6'b????1?: y = a[1];
6'b???1??: y = a[2];
6'b??1???: y = a[3];
6'b?1????: y = a[4];
6'b1?????: y = a[5];
6'b000000: y = a[6];
endcase
end
endmodule
module top (input [1:0] s, input [7:0] a, b, c, d, output reg [7:0] y);
module top (input [1:0] s, input [5:0] a, b, c, d, output reg [5:0] y);
always @* begin
case (s)
0: y = a;
......
module top (input [4:0] s, input [2:0] a, b, c, d, e, output reg [2:0] y);
always @* begin
(* parallel_case, full_case *)
casez (s)
5'b????1: y = a;
5'b???1?: y = b;
5'b??1??: y = c;
5'b?1???: y = d;
5'b1????: y = e;
endcase
end
endmodule
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