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yosys-tests
Commit a5b30e54 by SergeyDegtyar
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First tests for pilot project

parent 3e1e4f91
Showing with 1578 additions and 1 deletions
simple/Makefile
......@@ -19,4 +19,35 @@ endef
$(eval $(call template,alu,gates luts))
# DFF with constant drivers
$(eval $(call template,dff, dff))
$(eval $(call template,dffr, dff))
$(eval $(call template,dffc, dff))
$(eval $(call template,dffcp, dff))
$(eval $(call template,dffsr, dff))
# Tri-state buffers general use
$(eval $(call template,tristate, tristate))
$(eval $(call template,tristate_case, tristate))
$(eval $(call template,tristate_if, tristate))
$(eval $(call template,tristate_proc_asmt, tristate))
# Tri-state buffers with constant
$(eval $(call template,tristate_const_0, tristate))
$(eval $(call template,tristate_const_1, tristate))
$(eval $(call template,tristate_const_data, tristate))
# Demoting I/O port
$(eval $(call template,inout_port, tristate))
$(eval $(call template,inout_port_demote, tristate))
# MACC cells
$(eval $(call template,macc, macc))
#FSM with unreachable state
$(eval $(call template,fsm_unreach, fsm))
# Optimization of FSM when signal connected to input/input and output
$(eval $(call template,fsm, fsm))
$(eval $(call template,fsm_opt, fsm))
.PHONY: all clean
simple/dff/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.clk (clk ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 1)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end
endmodule
simple/dff/top.v 0 → 100644
module dff (clk, d, q);
input clk;
input d;
output reg q;
always @(posedge clk)
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dff u_dff (
.clk (clk ),
.d (1'b0 ),
.q (b )
);
endmodule
simple/dffc/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA;
reg dinC;
wire dinB;
top uut (
.clk (clk ),
.a (dinA ),
.c (dinC),
.b (dinB )
);
initial begin
dinC <= 1;
#5
dinC <= 0;
#10
dinC <= 1;
#10
dinC <= 0;
end
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 0)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end
endmodule
simple/dffc/top.v 0 → 100644
module dffcp
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
input c,
output b
);
dffcp u_dffcp (
.clk (clk ),
.clr (c ),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple/dffcp/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.clk (clk ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 0)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end
endmodule
simple/dffcp/top.v 0 → 100644
module dffcp
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, posedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffcp u_dffcp (
.clk (clk ),
.clr (1'b0),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple/dffr/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.clk (clk ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 1)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end
endmodule
simple/dffr/top.v 0 → 100644
module dffr
( input d, clk, rst, output reg q );
always @( posedge clk )
if ( rst )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffr u_dffr (
.clk (clk),
.rst (1'b1),
.d (a ),
.q (b )
);
endmodule
simple/dffsr/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.clk (clk ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 0)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end
endmodule
simple/dffsr/top.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffsr u_dffsr (
.clk (clk ),
.clr (1'b1),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple/fsm/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a;
reg b;
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
a <= 1;
b <= 0;
#50
a <= 0;
b <= 0;
#50
a <= 0;
b <= 1;
#50
a <= 1;
b <= 1;
end
endmodule
simple/fsm/top.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple/fsm_opt/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a;
reg b;
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
a <= 1;
b <= 0;
#50
a <= 0;
b <= 0;
#50
a <= 0;
b <= 1;
#50
a <= 1;
b <= 1;
end
endmodule
simple/fsm_opt/top.v 0 → 100644
module fsm (
clock,
reset,
req,
gnt
);
input clock,reset;
input [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g ;
wire [1:0] r ;
fsm u_fsm ( .clock(clk),
.reset(rst),
.req(r),
.gnt(g));
assign g0 = g[0];
assign g1 = g[1];
assign a = r[0];
assign b = r[1];
endmodule
simple/fsm_unreach/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] a;
reg [4:0] b;
reg [4:0] c;
reg rst;
wire [4:0] x;
wire [4:0] y;
wire [4:0] z;
top uut (
.clk (clk),
.rst (rst),
.a (a),
.b (b),
.c (c),
.x(x),
.y(y),
.z(z)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
a <= 4'b1111;
b <= 4'b1010;
c <= 4'b1011;
#50
a <= 4'b1000;
b <= 4'b1100;
c <= 4'b1010;
#50
a <= 4'b1100;
b <= 4'b0100;
c <= 4'b1011;
#50
a <= 4'b1101;
b <= 4'b1110;
c <= 4'b0000;
end
endmodule
simple/fsm_unreach/top.v 0 → 100644
module top(clk, rst, a, b, c, x, y, z);
input clk, rst;
input [4:0] a;
input [4:0] b;
input [4:0] c;
output reg [4:0] x;
output reg [4:0] y;
output reg [4:0] z;
reg [3:0] state;
always @(posedge clk) begin
if (rst) begin
x <= 1;
y <= 2;
z <= 3;
state <= 1;
end else begin
case (state)
1: begin
x <= x;
y <= b;
z <= 1;
end
2: begin
x <= a;
y <= c;
z <= c;
if ((x) < (5'd3)) state <= 4;
if ((y) < (5'd3)) state <= 3;
end
3: begin
x <= y;
y <= a;
z <= y;
state <= 1;
end
4: begin
x <= b;
y <= 5'd1;
z <= 5'd2;
end
5: begin
x <= 5'd1;
y <= 5'd2;
z <= z;
end
6: begin
x <= 5'd1;
y <= 5'd2;
z <= z;
end
endcase
end
end
endmodule
simple/inout_port/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire [1:0] dinB;
wire [1:0] dinC;
top uut (
.en (en ),
.a (dinA ),
.b (dinB ),
.c (dinC )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB[0]));
assert c_test(.en(en), .A(dinA), .B(dinC[0]));
assert cz_test(.en(!en), .A(1'bZ), .B(dinC[0]));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/inout_port/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
always @(en or i)
io[0] <= (en)? i : 1'bZ;
always @(en or i)
io[1] <= (i)? en : 1'bZ;
assign o = io;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
simple/inout_port_demote/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire [1:0] dinB;
wire [1:0] dinC;
top uut (
.en (en ),
.a (dinA ),
.b (dinB ),
.c (dinC )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB[0]));
assert c_test(.en(en), .A(dinA), .B(dinC[0]));
assert cz_test(.en(!en), .A(1'bZ), .B(dinC[0]));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/inout_port_demote/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
always @(en or i)
io[0] <= (en)? i : 1'bZ;
always @(en or i)
io[1] <= (i)? en : 1'bZ;
assign o = (en)? io : 2'bZZ;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
simple/macc/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [24:0] dinA;
reg [17:0] dinB;
reg carryin;
reg rst;
top uut (
.p (p),
.a (dinA),
.b (dinB),
.carryin (carryin ),
.clk (clk),
.rst (rst)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
dinA <= 38;
dinB <= 22;
carryin <= 1;
#50
dinA <= 0;
dinB <= 0;
carryin <= 0;
#50
dinA <= 33;
dinB <= 12;
carryin <= 0;
#50
dinA <= 0;
dinB <= 0;
carryin <= 0;
end
endmodule
simple/macc/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple/run.sh
......@@ -9,7 +9,7 @@ mkdir $1/work_$2
cd $1/work_$2
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v synth.v
iverilog -o testbench ../testbench.v synth.v ../../../../../techlibs/common/simcells.v
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
......
simple/scripts/dff.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple/scripts/fsm.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt
fsm_opt
synth -top top
write_verilog synth.v
simple/scripts/macc.ys 0 → 100644
read_verilog ../top.v
proc
alumacc
maccmap -unmap
synth -top top
write_verilog synth.v
simple/scripts/tristate.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -top top
write_verilog synth.v
simple/tristate/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.en (en ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple/tristate_case/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.en (en ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_case/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output o;
always @(en or i)
begin
case (en)
1:o <= i;
default :o <= 1'bZ;
endcase
end
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple/tristate_const_0/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.en (en ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A === B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_const_0/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (1'b0 ),
.i (a ),
.o (b )
);
endmodule
simple/tristate_const_1/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.en (en ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A !== B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_const_1/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (1'b1 ),
.i (a ),
.o (b )
);
endmodule
simple/tristate_const_data/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.en (en ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_const_data/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (1'bZ ),
.o (b )
);
endmodule
simple/tristate_if/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.en (en ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_if/top.v 0 → 100644
module tribuf (en, i, o);
input en;
input i;
output o;
always @*
begin
if (en)
o = i;
else
o = 1'bZ;
end
endmodule
module top (
input en,
input a,
output b
);
tribuf u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple/tristate_proc_asmt/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire dinB;
top uut (
.en (en ),
.a (dinA ),
.b (dinB )
);
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert b_test(.en(en), .A(dinA), .B(dinB));
endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_proc_asmt/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output o;
assign o = (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
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