Revert "Fix tests in backends,regression for new Yosys revision; Add new tests to frontends,misc,regression;"

This reverts commit e9fb66a3.

This reverts commit c9a8d4a8.

This reverts commit a5f93399.

Fix tests in backends,regression for new Yosys revision; Add new tests to frontends,misc,regression;

Add new tests to backends and architecture;
Merge commit "Add regression test for Yosys PR 896"

Signed-off-by: David Shah <dave@ds0.me>

issue_00865 - test failed (should be ok after merge
https://github.com/YosysHQ/yosys/pull/866)

'a'.

testing problems:
Issue #61 does not contain enough info.
Issues #82 and #83 I skipped because of errors.

---------------------

All of tasks will go to group regression, please change naming
convention there so files are named according to issue number (for
example issue_86 for directory and issue_86.ys script)
directory should contain exact example from issue, or in case it was
just generally described you can create your own example according to
explanation.

Idea for these tasks is not getting greater coverage  but making sure
old issues fixed are never broken again. Usually problem was failing of
yosys to generate any kind of output, in most of cases bellow, so just
checking if yosys did not assert any error is enough at least for these.
Issues bellow are taken from last two pages on issue tracker. Some of
these can really be trivial, and issue contains all info you need. Some
maybe need more thinking to be sure that you understood issue correctly.
In any case you are free to continue going trough the list of issues and
select new from it to cover.
I will see to crate some online spreadsheet that will have issue number,
type (if it is something that needed to be fixed or was a new feature or
some user error, and will have a status if it is covered by test or not.
That way we can have better overview what is going on.
So if you see that something is without a way to reproduce, or it was
user error just skip it, and when we have a spreadsheet we can update
there.

1. https://github.com/YosysHQ/yosys/issues/86
2. https://github.com/YosysHQ/yosys/issues/85
3. https://github.com/YosysHQ/yosys/issues/84
4. https://github.com/YosysHQ/yosys/issues/83
5. https://github.com/YosysHQ/yosys/issues/82
6. https://github.com/YosysHQ/yosys/issues/81
7. https://github.com/YosysHQ/yosys/issues/78
8. https://github.com/YosysHQ/yosys/issues/71
9. https://github.com/YosysHQ/yosys/issues/67
10. https://github.com/YosysHQ/yosys/issues/65
11. https://github.com/YosysHQ/yosys/issues/61
12. https://github.com/YosysHQ/yosys/issues/59
13. https://github.com/YosysHQ/yosys/issues/41
14. https://github.com/YosysHQ/yosys/issues/18

1. Add tests for synth_anlogic command
Now this tests are commented because of:
+ iverilog -o testbench ../testbench.v synth.v ../../common.v
../../../../../techlibs/common/simcells.v
../../../../../techlibs/anlogic/cells_sim.v
../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to bind
wire/reg/memory `A' in `testbench.uut._09_'
../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to
elaborate r-value: (INIT)>>(A)
2 error(s) during elaboration.

2. Add 'regression' test