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yosys-tests
Commit 2d606f87 by SergeyDegtyar
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Revert "Fix tests in backends,regression for new Yosys revision; Add new tests… 

Revert "Fix tests in backends,regression for new Yosys revision; Add new tests to frontends,misc,regression;"

This reverts commit e9fb66a3.
parent 4da141ba
Showing with 108 additions and 149 deletions
backends/Makefile
......@@ -38,7 +38,7 @@ $(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
#write_firrtl
$(eval $(call template,write_firrtl,write_firrtl))
$(eval $(call template,write_firrtl,write_firrtl write_firrtl))
#write_firrtl_mem_wr - issue #938
#terminate called after throwing an instance of 'std::out_of_range'
# what(): dict::at()
......@@ -48,7 +48,6 @@ $(eval $(call template,write_firrtl_logic,write_firrtl ))
$(eval $(call template,write_firrtl_reduce,write_firrtl ))
$(eval $(call template,write_firrtl_shift,write_firrtl ))
$(eval $(call template,write_firrtl_shiftx,write_firrtl ))
$(eval $(call template,write_firrtl_paramod,write_firrtl))
#write_ilang
$(eval $(call template,write_ilang,write_ilang write_ilang_selected))
......
backends/scripts/write_firrtl.ys
read_verilog ../top.v
proc
write_firrtl firrtl.firrtl
synth
write_firrtl firrtl2.firrtl
write_verilog synth.v
write_verilog synth.v
backends/write_edif/top.v
......@@ -7,9 +7,7 @@ module top
output reg A,
output reg cout
);
wire bb_out;
initial begin
A = 0;
cout = 0;
......@@ -26,16 +24,12 @@ end
assign {cout,A} = cin - y * x;
`endif
bb ubb (cin,y,x,bb_out);
bb ubb (cin,y,x);
endmodule
(* black_box *) module bb(in1, in2, clk, out1);
(* black_box *) module bb(in1, in2, clk);
input in1;
input in2;
input clk;
output reg out1;
always @(posedge clk)
out1 <= in1 & in2;
endmodule
frontends/Makefile
......@@ -76,18 +76,4 @@ $(eval $(call template,verilog_defaults,verilog_defaults verilog_defaults_push v
#verilog_defines
$(eval $(call template,verilog_defines,verilog_defines verilog_defines_val verilog_defines_u verilog_defines_d verilog_defines_u_val))
#verilog_lexer
$(eval $(call template,verilog_lexer_specify_specparam,verilog_lexer))
$(eval $(call template,verilog_lexer_package,verilog_lexer))
$(eval $(call template,verilog_lexer_interface_logic,verilog_lexer))
$(eval $(call template,verilog_lexer_casez,verilog_lexer))
$(eval $(call template,verilog_lexer_automatic_task,verilog_lexer))
$(eval $(call template,verilog_lexer_unique_priority,verilog_lexer))
$(eval $(call template,verilog_lexer_always_ff_latch,verilog_lexer))
$(eval $(call template,verilog_lexer_assert_assume_restrict,verilog_lexer_assert))
#../top.v:88: ERROR: syntax error, unexpected TOK_TYPEDEF
#$(eval $(call template,verilog_lexer_enum_typedef,verilog_lexer))
#../top.v:90: ERROR: syntax error, unexpected TOK_SUPPLY1
#$(eval $(call template,verilog_lexer_supply,verilog_lexer))
.PHONY: all clean
misc/Makefile
......@@ -52,7 +52,7 @@ $(eval $(call template,scc_hier_feedback, scc scc_all_cell_types scc_expect scc_
$(eval $(call template,scatter, scatter ))
#rename
$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat rename_wire rename_top_top rename_low))
$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat rename_wire))
#qwp
#qwp_v - exception (issue #923)
......@@ -182,18 +182,5 @@ $(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux
#hilomap
$(eval $(call template,hilomap, hilomap hilomap_hicell hilomap_locell hilomap_singleton hilomap_hicell_singleton hilomap_locell_singleton hilomap_hicell_locell_singleton))
#cutpoint
$(eval $(call template,cutpoint, cutpoint cutpoint_undef))
#mutate
$(eval $(call template,mutate, mutate_list mutate_cnot1 mutate_cnot0 mutate_const1 mutate_const0 mutate_inv mutate_all mutate_list_cfg mutate_list_ctrl mutate_list_none mutate_list_o mutate_list_seed mutate_list_s))
$(eval $(call template,mutate_mem, mutate_list mutate_all))
#fmconbine
$(eval $(call template,fmcombine, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd))
#pmuxtree
$(eval $(call template,pmuxtree, pmuxtree))
.PHONY: all clean
misc/rename/top.v
......@@ -28,10 +28,6 @@ module middle
input y,
output o
);
wire dd;
assign o = x + y;
endmodule
module low ();
endmodule
regression/Makefile
......@@ -29,8 +29,8 @@ $(eval $(call template,issue_00041,issue_00041))
#issue_00059
$(eval $(call template,issue_00059,issue_00059))
#issue_00065 - 27_04 test hangs up
#$(eval $(call template,issue_00065,issue_00065))
#issue_00065
$(eval $(call template,issue_00065,issue_00065))
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
......@@ -297,7 +297,7 @@ $(eval $(call template,issue_00763,issue_00763))
#issue_00767
$(eval $(call template,issue_00767,issue_00767))
#issue_00774 -takes too much time
#issue_00774
#$(eval $(call template,issue_00774,issue_00774))
#issue_00781
......@@ -336,29 +336,10 @@ $(eval $(call template,issue_00857,issue_00857))
#issue_00862
$(eval $(call template,issue_00862,issue_00862))
#issue_00865
#issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
$(eval $(call template,issue_00865,issue_00865))
#issue_00867
$(eval $(call template,issue_00867,issue_00867))
#issue_00870
$(eval $(call template,issue_00870,issue_00870))
#issue_00873
$(eval $(call template,issue_00873,issue_00873))
#issue_00888
$(eval $(call template,issue_00888,issue_00888))
#issue_00896
$(eval $(call template,issue_00896,issue_00896))
#issue_00922
$(eval $(call template,issue_00922,issue_00922))
#issue_00931
$(eval $(call template,issue_00931,issue_00931))
$(eval $(call template,pr_00896,pr_00896))
.PHONY: all clean
regression/issue_00059/testbench.v
......@@ -13,11 +13,10 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
.b (clk )
);
endmodule
regression/issue_00059/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
endmodule
regression/issue_00067/testbench.v
......@@ -13,11 +13,10 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
.b (clk )
);
endmodule
regression/issue_00067/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
endmodule
regression/issue_00071/testbench.v
......@@ -13,11 +13,10 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
.b (clk )
);
endmodule
regression/issue_00071/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
endmodule
regression/issue_00078/testbench.v
......@@ -13,11 +13,10 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
.b (clk )
);
endmodule
regression/issue_00078/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
endmodule
regression/issue_00081/testbench.v
......@@ -13,11 +13,10 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
.b (clk )
);
endmodule
regression/issue_00081/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
endmodule
regression/issue_00085/testbench.v
......@@ -13,11 +13,10 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
.b (clk )
);
endmodule
regression/issue_00085/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
endmodule
regression/issue_00086/testbench.v
......@@ -13,11 +13,10 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
.b (clk )
);
endmodule
regression/issue_00086/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
endmodule
regression/issue_00088/testbench.v
......@@ -13,11 +13,10 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
.b (clk )
);
endmodule
regression/issue_00088/top.v
parameter X = 2;
module top(b,c);
module top(b);
input b;
output c;
parameter Y = 3;
assign c = b;
endmodule
regression/pr_00896/outreg.v 0 → 100644
module dut(
input fast_clk, slow_clk,
input [3:0] waddr, raddr,
input [3:0] wdata,
input wen,
output [3:0] rdata
);
reg [3:0] mem[0:15];
reg [3:0] raddr_reg;
always @(posedge fast_clk) begin
if (wen)
mem[waddr] <= wdata;
end
always @(posedge slow_clk)
raddr_reg <= raddr;
assign rdata = mem[raddr_reg];
endmodule
regression/pr_00896/testbench.v 0 → 100644
`include "../outreg.v"
module tb;
reg fast_clk, slow_clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, tb);
repeat (80) @(posedge slow_clk);
$display("OKAY");
$finish;
end
always #4 fast_clk = (fast_clk === 1'b0);
always #12 slow_clk = (slow_clk === 1'b0);
reg [7:0] wdata = 1;
always @(posedge fast_clk) wdata <= {wdata[6:0], wdata[7] ^ wdata[2]};
reg [3:0] waddr = 0;
always @(posedge fast_clk) waddr <= waddr + 1'b1;
reg [3:0] raddr = 0;
always @(posedge slow_clk) raddr <= raddr + 1'b1;
wire [3:0] rdata, rdata_postsyn;
dut dut_i(
.fast_clk(fast_clk), .slow_clk(slow_clk),
.raddr(raddr), .waddr(waddr), .wen(1'b1),
.wdata(wdata[3:0]), .rdata(rdata)
);
dut_syn dut_syn_i(
.fast_clk(fast_clk), .slow_clk(slow_clk),
.raddr(raddr), .waddr(waddr), .wen(1'b1),
.wdata(wdata[3:0]), .rdata(rdata_postsyn)
);
always @(posedge fast_clk)
if (rdata_postsyn != rdata) begin
$display("ERROR");
$finish;
end
endmodule
regression/run.sh
......@@ -73,13 +73,7 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00835" ] ||\
[ "$1" = "issue_00857" ] ||\
[ "$1" = "issue_00862" ] ||\
[ "$1" = "issue_00865" ] ||\
[ "$1" = "issue_00867" ] ||\
[ "$1" = "issue_00870" ] ||\
[ "$1" = "issue_00873" ] ||\
[ "$1" = "issue_00888" ] ||\
[ "$1" = "issue_00922" ] ||\
[ "$1" = "issue_00931" ]; then
[ "$1" = "issue_00865" ]; then
expected_string=""
expected="1"
......@@ -97,8 +91,7 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00689" ] ||\
[ "$1" = "issue_00708" ] ||\
[ "$1" = "issue_00826" ] ||\
[ "$1" = "issue_00862" ] ||\
[ "$1" = "issue_00870" ]; then
[ "$1" = "issue_00862" ]; then
expected_string="Successfully finished Verilog frontend"
elif [ "$1" = "issue_00655" ]; then
expected_string="Executing EDIF backend"
......@@ -124,18 +117,6 @@ elif [ "$1" = "issue_00502" ] ||\
expected_string="_DFF_P_ 1"
elif [ "$1" = "issue_00865" ]; then
expected_string="FDRE 14"
elif [ "$1" = "issue_00867" ]; then
expected_string="RAMB36E1 1"
elif [ "$1" = "issue_00873" ]; then
expected_string="has an unprocessed 'init' attribute."
expected="0"
elif [ "$1" = "issue_00888" ]; then
expected_string="FDRE 4"
elif [ "$1" = "issue_00922" ]; then
expected_string="ERROR: Unclocked write port 0 on memory top.ram."
expected="0"
elif [ "$1" = "issue_00931" ]; then
expected_string="Number of cells: 5"
fi
yosys -ql yosys.log ../../scripts/$2.ys;
......@@ -169,7 +150,7 @@ else
[ "$1" = "issue_00589" ] ||\
[ "$1" = "issue_00628" ]; then
iverilog_adds="../../../../../techlibs/ice40/cells_sim.v"
elif [ "$1" = "issue_00896" ]; then
elif [ "$1" = "pr_00896" ]; then
iverilog_adds="../../../../../techlibs/ecp5/cells_sim.v"
fi
......
regression/scripts/pr_00896.ys 0 → 100644
read_verilog ../outreg.v
synth_ecp5
rename dut dut_syn
write_verilog -norename synth.v
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