1. 14 Jan, 2020 1 commit
  2. 06 Jan, 2020 1 commit
  3. 03 Jan, 2020 1 commit
  4. 23 Dec, 2019 1 commit
  5. 11 Dec, 2019 1 commit
  6. 28 Nov, 2019 1 commit
  7. 27 Nov, 2019 1 commit
  8. 24 Nov, 2019 1 commit
  9. 15 Nov, 2019 1 commit
  10. 06 Nov, 2019 1 commit
  11. 04 Sep, 2019 2 commits
  12. 03 Sep, 2019 1 commit
  13. 02 Sep, 2019 1 commit
  14. 27 Aug, 2019 1 commit
  15. 18 Aug, 2019 1 commit
  16. 14 Aug, 2019 1 commit
  17. 13 Aug, 2019 3 commits
  18. 08 Aug, 2019 1 commit
  19. 03 Aug, 2019 1 commit
  20. 31 Jul, 2019 1 commit
    • [VTA] VTA Compilation Script for Intel FPGA (#3494) · 83591aa5
      * initial compilation script for chisel-vta;
      
      * replace tabs with spaces;
      
      * compile script for de10-nano;
      
      * remove generated verilog source code;
      
      * remove `altsource_probe`, `debounce`, `edge_detect` ip;
      
      * replace quartus project files with a single tcl script;
      
      * Update install.md
      
      * improved makefile-based compilation script;
      
      * complete makefile-based compilation of chisel-vta for de10-nano;
      
      * install quartus;
      
      * conversion to .rbf file;
      
      * document chisel-vta compilation process for de10-nano;
      
      * rename generated bitstream file;
      
      * download and extract custom ip for de10-nano;
      
      * minor change
      
      * minor change
      
      * fix indentation;
      
      * bug fix;
      
      * improved robustness in makefile;
      
      * clean up;
      
      * add `.sdc .ipx .qsys` allowance in jenkins;
      
      * add ASF header;
      
      * add ASF header;
      
      * remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys;
      
      * add ASF header;
      
      * keep sources compact;
      
      * keep sources compact;
      
      * it's not necessary now
      
      * AXI4LiteClient -> AXI3Client for IntelShell
      
      * remove connection to fpga_only_master;
      
      * a few important bug fix: wire reset pin, and set host_r_last to high
      
      * remove intel specific interface definition;
      
      * add NO_DSP option in Makefile;
      
      * AXI4Lite is not used in IntelShell;
      
      * minor fix: disable dsp and use logic instead;
      
      * quartus version change: 18.0 -> 18.1
      
      * remove altera related statement;
      
      * compose compile_design.tcl
      
      * initial tcl script for soc_system generation;
      
      * remove .qsys file;
      
      * remove unused;
      
      * .qsys can be generated by tcl script;
      
      * remove hps_io and shrink size of soc_system;
      
      * integrate into makefile;
      
      * version change: 18.0 -> 18.1
      
      * add sample config file for de10-nano;
      
      * parameterize DEVICE and PROJECT_NAME
      
      * remove extra lines;
      
      * brief description on flashing sd card image for de10-nano
      
      * docs on building additional components
      
      * parameterize DEVICE and DEVICE_FAMILY
      
      * parameterize DEVICE and DEVICE_FAMILY
      
      * parameterize DEVICE and DEVICE_FAMILY
      
      * de10-nano -> de10nano
      
      * minor change
      
      * add comment in code and document in order to address review comments;
      Liangfu Chen committed
  21. 30 Jul, 2019 1 commit
  22. 29 Jul, 2019 2 commits
    • [VTA] Refactor to increase platform coverage (Ultra96 etc.) (#3496) · f55609b4
      * hardware refactor for increased FPGA coverage, small optimizations
      
      * fix header
      
      * cleaning up parameters that won't be needed for now
      
      * streamlining makefile, and simplifying tcl scripts
      
      * moving parameter derivation into pkg_config.py, keeping tcl scripts lightweight
      
      * refactoring tcl script to avoid global variables
      
      * deriving AXI signals in pkg_config.py
      
      * unifying address map definition for hardware and software drivers
      
      * single channel design for ultra96 to simplify build
      
      * enable alu by default, no mul opcode for now
      
      * hardware fix
      
      * new bitstream; vta version
      
      * avoid error when env variable is not set
      
      * ultra96 cleanup
      
      * further cleaning up tcl script for bitstream generation
      
      * preliminary rpc server support on ultra96
      
      * rpc server tracker scripts
      
      * ultra96 ldflag
      
      * ultra96 support
      
      * ultra96 support
      
      * cleanup line
      
      * cmake support for ultra96
      
      * simplify memory instantiation
      
      * cleaning up IP parameter initialization
      
      * fix queue instantiation
      
      * 2019.1 transition
      
      * fix macro def
      
      * removing bus width from config
      
      * cleanup
      
      * fix
      
      * turning off testing for now
      
      * cleanup ultra96 ps insantiation
      
      * minor refactor
      
      * adding comments
      
      * upgrading to tophub v0.6
      
      * model used in TVM target now refers to a specific version of VTA for better autoTVM scheduling
      
      * revert change due to bug
      
      * rename driver files to be for zynq-type devices
      
      * streamlining address mapping
      
      * unifying register map offset values between driver and hardware generator
      
      * rely on cma library for cache flush/invalidation
      
      * coherence management
      
      * not make buffer packing depend on data types that can be wider than 64bits
      
      * refactor config derivation to minimize free parameters
      
      * fix environment/pkg config interaction
      
      * adding cfg dump property to pkgconfig:
      
      * fix rpc reconfig
      
      * fix spacing
      
      * cleanup
      
      * fix spacing
      
      * long line fix
      
      * fix spacing and lint
      
      * fix line length
      
      * cmake fix
      
      * environment fix
      
      * renaming after pynq since the driver stack relies on the pynq library - see pynq.io
      
      * update doc
      
      * adding parameterization to  name
      
      * space
      
      * removing reg width
      
      * vta RPC
      
      * update doc on how to edit vta_config.json
      
      * fix path
      
      * fix path
      Thierry Moreau committed
  23. 28 Jul, 2019 2 commits
  24. 27 Jul, 2019 1 commit
  25. 26 Jul, 2019 1 commit
    • [VTA] [Chisel] support for different inp/wgt bits, rewrote DotProduct for clarity (#3605) · 87e18a44
      * support for different inp/wgt bits, rewrote dot for clarity
      
      * [VTA] [Chisel] support for different inp/wgt bits, rewrote DotProduct for clarity
      
      * [VTA] [Chisel] support for different inp/wgt bits, rewrote DotProduct for clarity
      
      * change back to sim
      
      * fix index
      
      * fix index
      
      * fix indent
      
      * fix indent
      
      * fix indent
      
      * fix trailing spaces
      
      * fix trailing spaces
      
      * change to more descriptive name
      
      * matric->matrix
      
      * fix spacing
      
      * fix spacing & added generic name for dot
      
      * better parameter flow
      
      * spacing
      
      * spacing
      
      * spacing
      
      * update requirement (tested) for dot, spacing
      
      * function call convention
      
      * small edit
      Benjamin Tu committed
  26. 23 Jul, 2019 1 commit
  27. 21 Jul, 2019 1 commit
  28. 17 Jul, 2019 1 commit
  29. 08 Jul, 2019 1 commit
    • [VTA] TSIM improvements and fixes (#3505) · a31dd162
      * add tsim init function
      
      * add sim device
      
      * test wait and resume
      
      * launch simulation thread from DPILoader
      
      * add VTASimDPI module to handle all simulation related stuff
      
      * test tsim init
      
      * move exit to simdpi module
      
      * update vta driver
      
      * add chisel DPI module
      
      * get back simshell
      
      * update vta to support dpi sim
      
      * update unittests
      
      * add tsim to integration-conv2d test
      
      * run resnet on tsim
      
      * remove max-cycles
      
      * match tsim counters with sim counters
      
      * use env in simulator to switch between sim and tsim
      
      * update unittest
      
      * rollback conv2d test
      
      * update resnet
      
      * add stats to matrix multiply
      
      * add stats
      
      * print stats after assert
      
      * update other tests
      
      * add stats to gemm
      
      * add return and remove unused libs
      
      * add missing arg
      
      * return lib
      
      * update comments for linter
      
      * add more comments to VTASimDPI module
      
      * remove trailing spaces
      
      * remove trailing spaces
      Luis Vega committed
  30. 20 Jun, 2019 1 commit
    • [VTA] Fix VTA function Vivado Compile Error. (#3375) · 917ad9f6
      Issue:
      when using vivado compile vta.cc with top function 'vta', vivado
      report deadlock error like '...with default size is used in a non -dataflow
      region, which may result in deadlock Please consider to resize the
      stream using the directive ‘set_directive_stream’ or the ‘HL S stream’
      pragma.'
      
      Solution:
      give the queue a default size as 8.
      Hua Jiang committed
  31. 14 Jun, 2019 1 commit
  32. 13 Jun, 2019 1 commit
  33. 11 Jun, 2019 1 commit
    • [VTA][TSIM] update app example (#3343) · 124f9b7f
      * add initial support to cycle counter to accelerator
      
      * remove prints from c
      
      * add event counter support to chisel tsim example
      
      * make it more readable
      
      * use a config class
      
      * update driver
      
      * add individual Makefile to chisel
      
      * add rule for installing vta package
      
      * add makefile for verilog backend
      
      * update drivers
      
      * update
      
      * rename
      
      * update README
      
      * put default sim back
      
      * set counter to zero
      Luis Vega committed
  34. 09 Jun, 2019 1 commit
  35. 07 Jun, 2019 1 commit