- 14 Jan, 2020 1 commit
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Liangfu Chen committed
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- 06 Jan, 2020 1 commit
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Kevin Yuan committed
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- 03 Jan, 2020 1 commit
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Liangfu Chen committed
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- 23 Dec, 2019 1 commit
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* [VTA][Chisel] End-to-end Inference with Chisel VTA * Update TensorAlu.scala
Liangfu Chen committed
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- 11 Dec, 2019 1 commit
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This PR tries to increase TSIM performance by introducing multi-threading support.
Liangfu Chen committed
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- 28 Nov, 2019 1 commit
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Liangfu Chen committed
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- 27 Nov, 2019 1 commit
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* disable pipelined adder and enable streamlined gemm execution * pipeline first layer of adder * explain difference between pipeadder and adder * add comment for explaining the hard-coded latency
Liangfu Chen committed
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- 24 Nov, 2019 1 commit
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* [LINT] Improve the check tool to handle ASF copyright message. * [LINT] Remove unnecessary copyright message as per ASF requirement. * Fix codegen hybrid * [LINT] Broaden license checks to include html, xml * [LINT] Fix rest of the files * Fix notice * [LINT] Improve check file type error message
Tianqi Chen committed
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- 15 Nov, 2019 1 commit
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* bug fix for padded load with large inputs * Update TensorLoad.scala * Update test_vta_insn.py
Liangfu Chen committed
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- 06 Nov, 2019 1 commit
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* Update TensorUtil.scala * Update test_vta_insn.py
Liangfu Chen committed
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- 04 Sep, 2019 2 commits
- 03 Sep, 2019 1 commit
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* [VTA] Fix TSIM compile error in Linux (add missing -fPIC flag); * [VTA] Fix TSIM compile error in Linux (add missing -fPIC flag); * fix indentation problem;
Liangfu Chen committed
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- 02 Sep, 2019 1 commit
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Luis Vega committed
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- 27 Aug, 2019 1 commit
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Liangfu Chen committed
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- 18 Aug, 2019 1 commit
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* [VTA][TSIM] parallel hardware compilation with macOS and debug support * simplify
Liangfu Chen committed
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- 14 Aug, 2019 1 commit
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* [VTA][Chisel] scale dram base address in hardware instead of runtime * remove trailing spaces
Luis Vega committed
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- 13 Aug, 2019 3 commits
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Benjamin Tu committed
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* [VTA][Chisel] run all unittests by default * better naming * add generated unittest folder to clean rule
Luis Vega committed -
* added alutest * fix indent * name change for cycle * improved data gen and infra * added alutest * fix indent * name change for cycle * improved data gen and infra * fix space * fix indent * fixes * aluRef * fix randomarary * add * Revert "add" This reverts commit 87077daebbe055dee11f80e37da3a6291138e0f0. * Revert "fix randomarary" This reverts commit df386c1e660eb6ebcff1a1f905610573676f1589. * Revert "aluRef" This reverts commit 8665f0d4a7b12b796b2cb1ca6bf9cfe5613ee389. * should fix dlmc-core
Benjamin Tu committed
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- 08 Aug, 2019 1 commit
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* fix * fixes
Benjamin Tu committed
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- 03 Aug, 2019 1 commit
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* added wholething * changed build and makefile
Benjamin Tu committed
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- 31 Jul, 2019 1 commit
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* initial compilation script for chisel-vta; * replace tabs with spaces; * compile script for de10-nano; * remove generated verilog source code; * remove `altsource_probe`, `debounce`, `edge_detect` ip; * replace quartus project files with a single tcl script; * Update install.md * improved makefile-based compilation script; * complete makefile-based compilation of chisel-vta for de10-nano; * install quartus; * conversion to .rbf file; * document chisel-vta compilation process for de10-nano; * rename generated bitstream file; * download and extract custom ip for de10-nano; * minor change * minor change * fix indentation; * bug fix; * improved robustness in makefile; * clean up; * add `.sdc .ipx .qsys` allowance in jenkins; * add ASF header; * add ASF header; * remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys; * add ASF header; * keep sources compact; * keep sources compact; * it's not necessary now * AXI4LiteClient -> AXI3Client for IntelShell * remove connection to fpga_only_master; * a few important bug fix: wire reset pin, and set host_r_last to high * remove intel specific interface definition; * add NO_DSP option in Makefile; * AXI4Lite is not used in IntelShell; * minor fix: disable dsp and use logic instead; * quartus version change: 18.0 -> 18.1 * remove altera related statement; * compose compile_design.tcl * initial tcl script for soc_system generation; * remove .qsys file; * remove unused; * .qsys can be generated by tcl script; * remove hps_io and shrink size of soc_system; * integrate into makefile; * version change: 18.0 -> 18.1 * add sample config file for de10-nano; * parameterize DEVICE and PROJECT_NAME * remove extra lines; * brief description on flashing sd card image for de10-nano * docs on building additional components * parameterize DEVICE and DEVICE_FAMILY * parameterize DEVICE and DEVICE_FAMILY * parameterize DEVICE and DEVICE_FAMILY * de10-nano -> de10nano * minor change * add comment in code and document in order to address review comments;
Liangfu Chen committed
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- 30 Jul, 2019 1 commit
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Thierry Moreau committed
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- 29 Jul, 2019 2 commits
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Luis Vega committed
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* hardware refactor for increased FPGA coverage, small optimizations * fix header * cleaning up parameters that won't be needed for now * streamlining makefile, and simplifying tcl scripts * moving parameter derivation into pkg_config.py, keeping tcl scripts lightweight * refactoring tcl script to avoid global variables * deriving AXI signals in pkg_config.py * unifying address map definition for hardware and software drivers * single channel design for ultra96 to simplify build * enable alu by default, no mul opcode for now * hardware fix * new bitstream; vta version * avoid error when env variable is not set * ultra96 cleanup * further cleaning up tcl script for bitstream generation * preliminary rpc server support on ultra96 * rpc server tracker scripts * ultra96 ldflag * ultra96 support * ultra96 support * cleanup line * cmake support for ultra96 * simplify memory instantiation * cleaning up IP parameter initialization * fix queue instantiation * 2019.1 transition * fix macro def * removing bus width from config * cleanup * fix * turning off testing for now * cleanup ultra96 ps insantiation * minor refactor * adding comments * upgrading to tophub v0.6 * model used in TVM target now refers to a specific version of VTA for better autoTVM scheduling * revert change due to bug * rename driver files to be for zynq-type devices * streamlining address mapping * unifying register map offset values between driver and hardware generator * rely on cma library for cache flush/invalidation * coherence management * not make buffer packing depend on data types that can be wider than 64bits * refactor config derivation to minimize free parameters * fix environment/pkg config interaction * adding cfg dump property to pkgconfig: * fix rpc reconfig * fix spacing * cleanup * fix spacing * long line fix * fix spacing and lint * fix line length * cmake fix * environment fix * renaming after pynq since the driver stack relies on the pynq library - see pynq.io * update doc * adding parameterization to name * space * removing reg width * vta RPC * update doc on how to edit vta_config.json * fix path * fix path
Thierry Moreau committed
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- 28 Jul, 2019 2 commits
- 27 Jul, 2019 1 commit
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* fix tensor issue/commit in gemm * remove trailing spaces
Luis Vega committed
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- 26 Jul, 2019 1 commit
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* support for different inp/wgt bits, rewrote dot for clarity * [VTA] [Chisel] support for different inp/wgt bits, rewrote DotProduct for clarity * [VTA] [Chisel] support for different inp/wgt bits, rewrote DotProduct for clarity * change back to sim * fix index * fix index * fix indent * fix indent * fix indent * fix trailing spaces * fix trailing spaces * change to more descriptive name * matric->matrix * fix spacing * fix spacing & added generic name for dot * better parameter flow * spacing * spacing * spacing * update requirement (tested) for dot, spacing * function call convention * small edit
Benjamin Tu committed
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- 23 Jul, 2019 1 commit
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Luis Vega committed
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- 21 Jul, 2019 1 commit
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Luis Vega committed
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- 17 Jul, 2019 1 commit
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Luis Vega committed
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- 08 Jul, 2019 1 commit
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* add tsim init function * add sim device * test wait and resume * launch simulation thread from DPILoader * add VTASimDPI module to handle all simulation related stuff * test tsim init * move exit to simdpi module * update vta driver * add chisel DPI module * get back simshell * update vta to support dpi sim * update unittests * add tsim to integration-conv2d test * run resnet on tsim * remove max-cycles * match tsim counters with sim counters * use env in simulator to switch between sim and tsim * update unittest * rollback conv2d test * update resnet * add stats to matrix multiply * add stats * print stats after assert * update other tests * add stats to gemm * add return and remove unused libs * add missing arg * return lib * update comments for linter * add more comments to VTASimDPI module * remove trailing spaces * remove trailing spaces
Luis Vega committed
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- 20 Jun, 2019 1 commit
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Issue: when using vivado compile vta.cc with top function 'vta', vivado report deadlock error like '...with default size is used in a non -dataflow region, which may result in deadlock Please consider to resize the stream using the directive ‘set_directive_stream’ or the ‘HL S stream’ pragma.' Solution: give the queue a default size as 8.
Hua Jiang committed
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- 14 Jun, 2019 1 commit
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Luis Vega committed
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- 13 Jun, 2019 1 commit
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* add support to event counters in VTA * fix comment * fix event-counter interface parameter * no longer needed * add sim back * add docs to event counters * fix docs * add more details about event counting * make dpi-module docs more accurate
Luis Vega committed
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- 11 Jun, 2019 1 commit
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* add initial support to cycle counter to accelerator * remove prints from c * add event counter support to chisel tsim example * make it more readable * use a config class * update driver * add individual Makefile to chisel * add rule for installing vta package * add makefile for verilog backend * update drivers * update * rename * update README * put default sim back * set counter to zero
Luis Vega committed
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- 09 Jun, 2019 1 commit
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Luis Vega committed
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- 07 Jun, 2019 1 commit
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* add documentation and check for extension * add env variable for verilator include * fix typo * this will test if path exist otherwise it won't buid * check if verilator path and binary is set properly * add ? * remove export * no longer needed
Luis Vega committed
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