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Commit 9a542e37 by Luis Vega Committed by Jared Roesch
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fix case when offset is odd and size is even (#3643)

parent da40645f
Showing with 1 additions and 1 deletions
vta/hardware/chisel/src/main/scala/core/LoadUop.scala
...@@ -76,7 +76,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { ...@@ -76,7 +76,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
val xcnt = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len)) val xcnt = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len))
val xlen = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len)) val xlen = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len))
val xrem = Reg(chiselTypeOf(dec.xsize)) val xrem = Reg(chiselTypeOf(dec.xsize))
val xsize = dec.xsize(0) + (dec.xsize >> log2Ceil(numUop)) - 1.U val xsize = (dec.xsize >> log2Ceil(numUop)) + dec.xsize(0) + (dec.sram_offset % 2.U) - 1.U
val xmax = (1 << mp.lenBits).U val xmax = (1 << mp.lenBits).U
val xmax_bytes = ((1 << mp.lenBits)*mp.dataBits/8).U val xmax_bytes = ((1 << mp.lenBits)*mp.dataBits/8).U
......
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