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wenyuanbo
tic
Commits
56996378
Commit
56996378
authored
Jan 14, 2020
by
Liangfu Chen
Committed by
Thierry Moreau
Jan 13, 2020
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[VTA] Fix an issue in updating uop_idx in the TensorGemm module (#4694)
parent
c69092ae
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vta/hardware/chisel/src/main/scala/core/TensorGemm.scala
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56996378
...
...
@@ -280,7 +280,7 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters)
(
state
===
sExe
&&
uop_idx
===
uop_end
-
1.
U
))
{
uop_idx
:=
dec
.
uop_begin
}.
elsewhen
(
state
===
sExe
)
{
}.
elsewhen
(
state
===
sExe
&&
dec
.
uop_begin
=/=
uop_end
)
{
uop_idx
:=
uop_idx
+
1.
U
}
...
...
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