[VTA][Chisel] End-to-end Inference with Chisel VTA (#4574)

* [VTA][Chisel] End-to-end Inference with Chisel VTA * Update TensorAlu.scala

[VTA][Chisel] End-to-end Inference with Chisel VTA (#4574)
* [VTA][Chisel] End-to-end Inference with Chisel VTA * Update TensorAlu.scala
dfc4009c · Liangfu Chen · Thierry Moreau · 79581dd7 · dfc4009c
Commit dfc4009c authored Dec 24, 2019 by Liangfu Chen Committed by Thierry Moreau Dec 23, 2019
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vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
+2 -1

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--- a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
+++ b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
@@ -230,7 +230,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
  tensorImm.data.valid := state === sReadTensorB
  tensorImm.data.bits.foreach { b =>
    b.foreach { c =>
-      c := dec.alu_imm
+      c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1),
+               Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm), dec.alu_imm)
    }
  }