[VTA] add doc to tsim-example driver and update verilator env variable (#3302)

* add documentation and check for extension

* add env variable for verilator include

* fix typo

* this will test if path exist otherwise it won't buid

* check if verilator path and binary is set properly

* add ?

* remove export

* no longer needed

vta/apps/tsim_example/python/tsim/driver.py

@@ -21,14 +21,27 @@ import json
 import os.path as osp
 from sys import platform
 
-def driver(hw, sw):
+def driver(hw_lib, sw_lib):
+    """Init hardware and software shared library for add-by-one accelerator
+
+     Parameters
+     ------------
+     hw_lib : str
+        Name of hardware shared library
+
+     sw_lib : str
+        Name of software shared library
+    """
     _cur_path = osp.dirname(osp.abspath(osp.expanduser(__file__)))
     _root_path = osp.join(_cur_path, "..", "..")
     _cfg_file = osp.join(_root_path, "config", "config.json")
     _cfg = json.load(open(_cfg_file))
-    _ext = ".dylib" if platform == "darwin" else ".so"
-    _hw_lib = osp.join(_root_path, _cfg['BUILD_NAME'], hw + _ext)
-    _sw_lib = osp.join(_root_path, _cfg['BUILD_NAME'], sw + _ext)
+    if not hw_lib.endswith(("dylib", "so")):
+        hw_lib += ".dylib" if platform == "darwin" else ".so"
+    if not sw_lib.endswith(("dylib", "so")):
+        sw_lib += ".dylib" if platform == "darwin" else ".so"
+    _hw_lib = osp.join(_root_path, _cfg['BUILD_NAME'], hw_lib)
+    _sw_lib = osp.join(_root_path, _cfg['BUILD_NAME'], sw_lib)
 
     def load_dll(dll):
         try:

vta/hardware/chisel/Makefile

@@ -15,6 +15,17 @@
 # specific language governing permissions and limitations
 # under the License.
 
+# Change this variable if Verilator is installed on a different location
+VERILATOR_INC_DIR ?= /usr/local/share/verilator/include
+
+ifeq (, $(shell which verilator))
+ $(error "No Verilator in $(PATH), consider doing apt-get install verilator")
+endif
+
+ifeq (, $(wildcard $(VERILATOR_INC_DIR)/*))
+ $(error "Verilator include directory is not set properly")
+endif
+
 CONFIG = DefaultF1Config
 TOP = VTA
 TOP_TEST = Test
@@ -25,7 +36,6 @@ VTA_LIBNAME = libvta_hw
 config_test = $(TOP_TEST)$(CONFIG)
 vta_dir = $(abspath ../../)
 tvm_dir = $(abspath ../../../)
-verilator_inc_dir = /usr/local/share/verilator/include
 verilator_build_dir = $(vta_dir)/$(BUILD_NAME)/verilator
 chisel_build_dir = $(vta_dir)/$(BUILD_NAME)/chisel
 
@@ -50,14 +60,14 @@ cxx_flags += -DVM_SC=0
 cxx_flags += -Wno-sign-compare
 cxx_flags += -include V$(TOP_TEST).h
 cxx_flags += -I$(verilator_build_dir)
-cxx_flags += -I$(verilator_inc_dir)
-cxx_flags += -I$(verilator_inc_dir)/vltstd
+cxx_flags += -I$(VERILATOR_INC_DIR)
+cxx_flags += -I$(VERILATOR_INC_DIR)/vltstd
 cxx_flags += -I$(vta_dir)/include
 cxx_flags += -I$(tvm_dir)/include
 cxx_flags += -I$(tvm_dir)/3rdparty/dlpack/include
 
-cxx_files = $(verilator_inc_dir)/verilated.cpp
-cxx_files += $(verilator_inc_dir)/verilated_dpi.cpp
+cxx_files = $(VERILATOR_INC_DIR)/verilated.cpp
+cxx_files += $(VERILATOR_INC_DIR)/verilated_dpi.cpp
 cxx_files += $(wildcard $(verilator_build_dir)/*.cpp)
 cxx_files += $(vta_dir)/hardware/dpi/tsim_device.cc
 
@@ -65,7 +75,7 @@ ifneq ($(USE_TRACE), 0)
   verilator_opt += --trace
   cxx_flags += -DVM_TRACE=1
   cxx_flags += -DTSIM_TRACE_FILE=$(verilator_build_dir)/$(TOP_TEST).vcd
-  cxx_files += $(verilator_inc_dir)/verilated_vcd_c.cpp
+  cxx_files += $(VERILATOR_INC_DIR)/verilated_vcd_c.cpp
 else
   cxx_flags += -DVM_TRACE=0
 endif