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Commit 83591aa5 by Liangfu Chen Committed by Thierry Moreau
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[VTA] VTA Compilation Script for Intel FPGA (#3494) 

* initial compilation script for chisel-vta;

* replace tabs with spaces;

* compile script for de10-nano;

* remove generated verilog source code;

* remove `altsource_probe`, `debounce`, `edge_detect` ip;

* replace quartus project files with a single tcl script;

* Update install.md

* improved makefile-based compilation script;

* complete makefile-based compilation of chisel-vta for de10-nano;

* install quartus;

* conversion to .rbf file;

* document chisel-vta compilation process for de10-nano;

* rename generated bitstream file;

* download and extract custom ip for de10-nano;

* minor change

* minor change

* fix indentation;

* bug fix;

* improved robustness in makefile;

* clean up;

* add `.sdc .ipx .qsys` allowance in jenkins;

* add ASF header;

* add ASF header;

* remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys;

* add ASF header;

* keep sources compact;

* keep sources compact;

* it's not necessary now

* AXI4LiteClient -> AXI3Client for IntelShell

* remove connection to fpga_only_master;

* a few important bug fix: wire reset pin, and set host_r_last to high

* remove intel specific interface definition;

* add NO_DSP option in Makefile;

* AXI4Lite is not used in IntelShell;

* minor fix: disable dsp and use logic instead;

* quartus version change: 18.0 -> 18.1

* remove altera related statement;

* compose compile_design.tcl

* initial tcl script for soc_system generation;

* remove .qsys file;

* remove unused;

* .qsys can be generated by tcl script;

* remove hps_io and shrink size of soc_system;

* integrate into makefile;

* version change: 18.0 -> 18.1

* add sample config file for de10-nano;

* parameterize DEVICE and PROJECT_NAME

* remove extra lines;

* brief description on flashing sd card image for de10-nano

* docs on building additional components

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* de10-nano -> de10nano

* minor change

* add comment in code and document in order to address review comments;
parent 5968eef2
Showing with 872 additions and 6 deletions
docs/vta/install.md
......@@ -179,10 +179,9 @@ The performance metrics measured on the Pynq board will be reported for each con
You can also try out our [VTA programming tutorials](https://docs.tvm.ai/vta/tutorials/index.html).
## VTA FPGA Toolchain Installation
This third and last guide allows users to generate custom VTA bitstreams using free-to-use Xilinx compilation toolchains.
This third and last guide allows users to generate custom VTA bitstreams using free-to-use Xilinx or Intel compilation toolchains.
### Xilinx Toolchain Installation
......@@ -234,7 +233,39 @@ export XILINX_VIVADO=${XILINX_PATH}/Vivado/2019.1
export PATH=${XILINX_VIVADO}/bin:${PATH}
```
### Custom VTA Bitstream Compilation
### Intel Toolchain Installation
It is recommended to use `Intel Quartus Prime 18.1`, since the test scripts contained in this document have been tested on this version.
You would need to install Intel's FPGA compilation toolchain, [Quartus Prime Lite](http://fpgasoftware.intel.com/?edition=lite), which is a license-free version of the Intel Quartus Prime software.
#### Obtaining and Launching the Quartus GUI Installer
1. Go to the [download center](http://fpgasoftware.intel.com/?edition=lite), and download the linux version of `Quartus Prime (include Nios II EDS)` and `Cyclone V device support` files in the `Separate file` tab. This avoid downloading unused device support files.
2. Sign in the form if you have an account, or register on the right side of the web page to create an account.
3. After signed in, you are able to download the installer and the device support files.
4. Now that the files are downloaded, go to your `Downloads` directory, and change the file permissions:
```bash
chmod u+x QuartusLiteSetup-18.1.0.625-linux.run
```
5. Now ensure both the installer and device support files are in the same directory, and you can run the install with:
```bash
./QuartusLiteSetup-18.1.0.625-linux.run
```
6. Follow the instructions on the pop-up GUI form, and install all the content in the `/usr/local` directory. After installation, `/usr/local/intelFPGA_lite/18.1` would be created and the Quartus program along with other programs would be available in the folder.
#### Environment Setup
Similar to what should be done for Xilinx toolchain, the following line should be added to your `~/.bashrc`.
```bash
# Intel Quartus 18.1 environment
export QUARTUS_ROOTDIR="/usr/local/intelFPGA_lite/18.1/quartus"
export PATH=${QUARTUS_ROOTDIR}/bin:${PATH}
export PATH=${QUARTUS_ROOTDIR}/sopc_builder/bin:${PATH}
```
This would add quartus binary path into your `PATH` environment variable, so you can launch compilation scripts from the command line.
### HLS-based Custom VTA Bitstream Compilation for PYNQ
High-level hardware parameters are listed in the VTA configuration file and can be customized by the user.
For this custom VTA bitstream compilation exercise, we'll change the frequency of our design, so it can be clocked a little faster.
......@@ -267,6 +298,72 @@ We recommend setting the `VTA_HW_COMP_THREADS` variable in the Makefile to take
Once the compilation completes, the generated bitstream can be found under `<tvm root>/vta/build/hardware/xilinx/vivado/<configuration>/export/vta.bit`.
### Chisel-based Custom VTA Bitstream Compilation for DE10-Nano
Similar to the HLS-based design, high-level hardware parameters in Chisel-based design are listed in the VTA configuration file [Configs.scala](https://github.com/dmlc/tvm/blob/master/vta/hardware/chisel/src/main/scala/core/Configs.scala), and they can be customized by the user.
For Intel FPGA, bitstream generation is driven by a top-level `Makefile` under `<tvmroot>/vta/hardware/intel`.
If you just want to generate the Chisel-based VTA IP core for the DE10-Nano board without compiling the design for the FPGA hardware, enter:
```bash
cd <tvmroot>/vta/hardware/intel
make ip
```
Then you'll be able to locate the generated verilog file at `<tvmroot>/vta/build/hardware/intel/chisel/<configuration>/VTA.DefaultDe10Config.v`.
If you would like to run the full hardware compilation for the `de10nano` board:
```bash
make
```
This process might be a bit lengthy, and might take up to half an hour to complete depending on the performance of your PC. The Quartus Prime software would automatically detect the number of cores available on your PC and try to utilize all of them to perform such process.
Once the compilation completes, the generated bistream can be found under `<tvmroot>/vta/build/hardware/intel/quartus/<configuration>/export/vta.rbf`. You can also open the Quartus project file (.qpf) available at `<tvmroot>/vta/build/hardware/intel/quartus/<configuration>/de10_nano_top.qpf` to look around the generated reports.
#### Flash SD Card and Boot Angstrom Linux
To flash SD card and boot Linux on DE10-Nano, it is recommended to navigate to the [Resource](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046&PartNo=4) tab of the DE10-Nano product page from Terasic Inc.
After registeration and login on the webpage, the prebuild Angstrom Linux image would be available for downloading and flashing.
Specifically, to flash the downloaded Linux SD card image into your physical SD card:
First, extract the gzipped archive file.
``` bash
tar xf de10-nano-image-Angstrom-v2016.12.socfpga-sdimg.2017.03.31.tgz
```
This would produce a single SD card image named `de10-nano-image-Angstrom-v2016.12.socfpga-sdimg` (approx. 2.4 GB), it contains all the file systems to boot Angstrom Linux.
Second, plugin a SD card that is ready to flash in your PC, and identify the device id for the disk with `fdisk -l`, or `gparted` if you feel better to use GUI. The typical device id for your disk would likely to be `/dev/sdb`.
Then, flash the disk image into your physical SD card with the following command:
``` bash
# NOTE: root privilege is typically required to run the following command.
dd if=de10-nano-image-Angstrom-v2016.12.socfpga-sdimg of=/dev/sdb status=progress
```
This would take a few minutes for your PC to write the whole file systems into the SD card.
After this process completes, you are ready to unmount the SD card and insert it into your DE10-Nano board.
Now you can connect the power cable and serial port to boot the Angstrom Linux.
#### Build Additional Components to Use VTA Bitstream
To use the above built bitstream on DE10-Nano hardware, several additional components need to be compiled for the system.
Specifically, to compile application executables for the system, you need to download and install [SoCEDS](http://fpgasoftware.intel.com/soceds/18.1/?edition=standard&download_manager=dlm3&platform=linux), or alternatively install the `g++-arm-linux-gnueabihf` package on your host machine. You would also need a `cma` kernel module to allocate contigous memory, and a driver for communicating with the VTA subsystem.
For easier program debugging (e.g. `metal_test` program at `vta/tests/hardware/metal_test`), it is also recommended to install `gdbserver` on you device. For instance, you can start your program on the device by runninng:
``` bash
gdbserver localhost:4444 ./metal_test
```
, and then you can set break points and print values of desired varilables on the host:
``` bash
gdb-multiarch --fullname metal_test
(gdb) target remote <device-ip>:4444
```
In addition, to enable fully featured VTA for DE10-Nano, you would also need `python3-numpy`, `python3-decorate`, `python3-attrs` to be cross-compiled.
### Use the Custom Bitstream
We can program the new VTA FPGA bitstream by setting the bitstream path of the `vta.program_fpga()` function in the tutorial examples, or in the `test_program_rpc.py` script.
......
tests/lint/add_asf_header.py
......@@ -130,6 +130,7 @@ FMT_MAP = {
"rst" : header_rststyle,
"gradle" : header_groovystyle,
"xml": header_mdstyle,
"tcl": header_pystyle,
}
def add_header(fname, header):
......
tests/lint/check_file_type.py
......@@ -68,6 +68,7 @@ ALLOW_EXTENSION = {
"sbt",
"properties",
"v",
"sdc",
# generated parser
"interp",
"tokens"
......
vta/config/de10nano_sample.json 0 → 100644
{
"TARGET" : "de10nano",
"HW_VER" : "0.0.1",
"LOG_INP_WIDTH" : 3,
"LOG_WGT_WIDTH" : 3,
"LOG_ACC_WIDTH" : 5,
"LOG_BATCH" : 0,
"LOG_BLOCK" : 4,
"LOG_UOP_BUFF_SIZE" : 15,
"LOG_INP_BUFF_SIZE" :15,
"LOG_WGT_BUFF_SIZE" : 18,
"LOG_ACC_BUFF_SIZE" : 17
}
vta/hardware/chisel/src/main/scala/core/Fetch.scala
......@@ -95,7 +95,7 @@ class Fetch(debug: Boolean = false)(implicit p: Parameters) extends Module {
}
is (sReadLSB) {
when (io.vme_rd.data.valid) {
state := sReadMSB
state := sReadMSB
}
}
is (sReadMSB) {
......
vta/hardware/chisel/src/main/scala/interface/axi/AXI.scala
......@@ -25,6 +25,7 @@ import vta.util.genericbundle._
case class AXIParams(
coherent: Boolean = false,
idBits: Int = 1,
addrBits: Int = 32,
dataBits: Int = 64,
lenBits: Int = 8,
......@@ -34,7 +35,6 @@ case class AXIParams(
require (addrBits > 0)
require (dataBits >= 8 && dataBits % 2 == 0)
val idBits = 1
val strbBits = dataBits/8
val sizeBits = 3
val burstBits = 2
......
vta/hardware/chisel/src/main/scala/shell/Configs.scala
......@@ -61,3 +61,16 @@ class F1Config extends Config((site, here, up) => {
vcrParams = VCRParams(),
vmeParams = VMEParams())
})
/** De10Config. Shell configuration for De10 */
class De10Config extends Config((site, here, up) => {
case ShellKey => ShellParams(
hostParams = AXIParams(
addrBits = 16, dataBits = 32, idBits = 13, lenBits = 4),
memParams = AXIParams(
addrBits = 32, dataBits = 64, userBits = 5,
lenBits = 4, // limit to 16 beats, instead of 256 beats in AXI4
coherent = true),
vcrParams = VCRParams(),
vmeParams = VMEParams())
})
vta/hardware/chisel/src/main/scala/shell/IntelShell.scala 0 → 100644
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
package vta.shell
import chisel3._
import vta.util.config._
import vta.interface.axi._
import vta.core._
/** IntelShell.
*
* The IntelShell is based on a VME, VCR and core. This creates a complete VTA
* system that can be used for simulation or real hardware.
*/
class IntelShell(implicit p: Parameters) extends Module {
val io = IO(new Bundle{
val host = new AXIClient(p(ShellKey).hostParams)
val mem = new AXIMaster(p(ShellKey).memParams)
})
val vcr = Module(new VCR)
val vme = Module(new VME)
val core = Module(new Core)
core.io.vcr <> vcr.io.vcr
vme.io.vme <> core.io.vme
// vcr.io.host <> io.host
io.host.aw.ready := vcr.io.host.aw.ready
vcr.io.host.aw.valid := io.host.aw.valid
vcr.io.host.aw.bits.addr := io.host.aw.bits.addr
io.host.w.ready := vcr.io.host.w.ready
vcr.io.host.w.valid := io.host.w.valid
vcr.io.host.w.bits.data := io.host.w.bits.data
vcr.io.host.w.bits.strb := io.host.w.bits.strb
vcr.io.host.b.ready := io.host.b.ready
io.host.b.valid := vcr.io.host.b.valid
io.host.b.bits.resp := vcr.io.host.b.bits.resp
io.host.b.bits.id := io.host.w.bits.id
io.host.ar.ready := vcr.io.host.ar.ready
vcr.io.host.ar.valid := io.host.ar.valid
vcr.io.host.ar.bits.addr := io.host.ar.bits.addr
vcr.io.host.r.ready := io.host.r.ready
io.host.r.valid := vcr.io.host.r.valid
io.host.r.bits.data := vcr.io.host.r.bits.data
io.host.r.bits.resp := vcr.io.host.r.bits.resp
io.host.r.bits.id := io.host.ar.bits.id
io.host.b.bits.user <> DontCare
io.host.r.bits.user <> DontCare
io.host.r.bits.last := 1.U
io.mem <> vme.io.mem
}
vta/hardware/chisel/src/main/scala/vta/Configs.scala
......@@ -34,6 +34,7 @@ import vta.test._
class DefaultPynqConfig extends Config(new CoreConfig ++ new PynqConfig)
class DefaultF1Config extends Config(new CoreConfig ++ new F1Config)
class DefaultDe10Config extends Config(new CoreConfig ++ new De10Config)
object DefaultPynqConfig extends App {
implicit val p: Parameters = new DefaultPynqConfig
......@@ -45,7 +46,22 @@ object DefaultF1Config extends App {
chisel3.Driver.execute(args, () => new XilinxShell)
}
object DefaultDe10Config extends App {
implicit val p: Parameters = new DefaultDe10Config
chisel3.Driver.execute(args, () => new IntelShell)
}
object TestDefaultPynqConfig extends App {
implicit val p: Parameters = new DefaultPynqConfig
chisel3.Driver.execute(args, () => new Test)
}
object TestDefaultF1Config extends App {
implicit val p: Parameters = new DefaultF1Config
chisel3.Driver.execute(args, () => new Test)
}
object TestDefaultDe10Config extends App {
implicit val p: Parameters = new DefaultDe10Config
chisel3.Driver.execute(args, () => new Test)
}
vta/hardware/intel/Makefile 0 → 100644
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
# regarding copyright ownership. The ASF licenses this file
# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
# Directories
ROOTDIR = $(CURDIR)
BUILD_NAME = build
BUILD_DIR = $(ROOTDIR)/../../$(BUILD_NAME)/hardware/intel
SCRIPT_DIR = $(ROOTDIR)/scripts
SRC_DIR = $(ROOTDIR)/../chisel
# Process VTA JSON config
VTA_CONFIG = python $(CURDIR)/../../config/vta_config.py
# Debug flag
DEBUG = false
# Prevent generation of DSP
NO_DSP = true
# Device
DEVICE = $(shell $(VTA_CONFIG) --get-fpga-dev)
# Device family
DEVICE_FAMILY = $(shell $(VTA_CONFIG) --get-fpga-family)
# Project name
PROJECT = de10_nano_top
#---------------------
# Compilation parameters
#--------------------
# Derive config name
CONF = $(shell ${VTA_CONFIG} --cfg-str)
IP_BUILD_PATH = $(BUILD_DIR)/chisel/$(CONF)
HW_BUILD_PATH = $(BUILD_DIR)/quartus/$(CONF)
ifeq ($(NO_DSP), true)
DSP_FLAG =
else
DSP_FLAG = --dsp
endif
# IP file path
IP_PATH = $(IP_BUILD_PATH)/VTA.DefaultDe10Config.v
# Bitstream file path
BIT_PATH = $(HW_BUILD_PATH)/export/vta.rbf
# System design file path
QSYS_PATH = $(HW_BUILD_PATH)/soc_system.qsys
.PHONY: all ip bit qsys clean
all: bit
ip: $(IP_PATH)
bit: $(BIT_PATH)
qsys: $(QSYS_PATH)
$(IP_PATH): $(SRC_DIR)
mkdir -p $(IP_BUILD_PATH)
cd $(SRC_DIR) && \
make CONFIG=DefaultDe10Config chisel_build_dir=$(IP_BUILD_PATH) verilog
$(QSYS_PATH): $(IP_PATH)
mkdir -p $(HW_BUILD_PATH)
cd $(HW_BUILD_PATH) && \
cp -r $(SCRIPT_DIR)/* $(HW_BUILD_PATH) && \
python3 $(SCRIPT_DIR)/set_attrs.py -i $(IP_PATH) -o $(HW_BUILD_PATH)/ip/vta/VTAShell.v $(DSP_FLAG) && \
qsys-script --script=soc_system.tcl $(DEVICE) $(DEVICE_FAMILY)
$(BIT_PATH): $(QSYS_PATH)
cd $(HW_BUILD_PATH) && \
quartus_sh -t $(SCRIPT_DIR)/compile_design.tcl $(DEVICE) $(PROJECT) && \
mkdir -p $(shell dirname $(BIT_PATH)) && \
quartus_cpf -c $(HW_BUILD_PATH)/$(PROJECT).sof $(BIT_PATH)
clean:
rm -rf $(BUILD_DIR)
vta/hardware/intel/README.md 0 → 100644
<!--- Licensed to the Apache Software Foundation (ASF) under one -->
<!--- or more contributor license agreements. See the NOTICE file -->
<!--- distributed with this work for additional information -->
<!--- regarding copyright ownership. The ASF licenses this file -->
<!--- to you under the Apache License, Version 2.0 (the -->
<!--- "License"); you may not use this file except in compliance -->
<!--- with the License. You may obtain a copy of the License at -->
<!--- http://www.apache.org/licenses/LICENSE-2.0 -->
<!--- Unless required by applicable law or agreed to in writing, -->
<!--- software distributed under the License is distributed on an -->
<!--- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -->
<!--- KIND, either express or implied. See the License for the -->
<!--- specific language governing permissions and limitations -->
<!--- under the License. -->
Complete instructions on how to build custom FPGA hardware designs are available on the [TVM documentation webpage](https://docs.tvm.ai/vta/install.html#vta-fpga-toolchain-installation).
vta/hardware/intel/scripts/de10_nano_top.v 0 → 100644
// Licensed to the Apache Software Foundation (ASF) under one
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
// to you under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// software distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//=======================================================
// This code is partially generated by Terasic System Builder
//=======================================================
module de10_nano_top(
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
//////////// HPS //////////
inout HPS_CONV_USB_N,
output [14: 0] HPS_DDR3_ADDR,
output [ 2: 0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CKE,
output HPS_DDR3_CS_N,
output [ 3: 0] HPS_DDR3_DM,
inout [31: 0] HPS_DDR3_DQ,
inout [ 3: 0] HPS_DDR3_DQS_N,
inout [ 3: 0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
//////////// LED //////////
output [ 7: 0] LED
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire hps_fpga_reset_n;
wire fpga_clk_50;
// connection of internal logics
assign fpga_clk_50 = FPGA_CLK1_50;
//=======================================================
// Structural coding
//=======================================================
soc_system u0(
//Clock&Reset
.clk_clk(FPGA_CLK1_50), // clk.clk
.reset_reset_n(hps_fpga_reset_n), // reset.reset_n
//HPS ddr3
.memory_mem_a(HPS_DDR3_ADDR), // memory.mem_a
.memory_mem_ba(HPS_DDR3_BA), // .mem_ba
.memory_mem_ck(HPS_DDR3_CK_P), // .mem_ck
.memory_mem_ck_n(HPS_DDR3_CK_N), // .mem_ck_n
.memory_mem_cke(HPS_DDR3_CKE), // .mem_cke
.memory_mem_cs_n(HPS_DDR3_CS_N), // .mem_cs_n
.memory_mem_ras_n(HPS_DDR3_RAS_N), // .mem_ras_n
.memory_mem_cas_n(HPS_DDR3_CAS_N), // .mem_cas_n
.memory_mem_we_n(HPS_DDR3_WE_N), // .mem_we_n
.memory_mem_reset_n(HPS_DDR3_RESET_N), // .mem_reset_n
.memory_mem_dq(HPS_DDR3_DQ), // .mem_dq
.memory_mem_dqs(HPS_DDR3_DQS_P), // .mem_dqs
.memory_mem_dqs_n(HPS_DDR3_DQS_N), // .mem_dqs_n
.memory_mem_odt(HPS_DDR3_ODT), // .mem_odt
.memory_mem_dm(HPS_DDR3_DM), // .mem_dm
.memory_oct_rzqin(HPS_DDR3_RZQ), // .oct_rzqin
//FPGA
.hps_0_h2f_reset_reset_n(hps_fpga_reset_n) // hps_0_h2f_reset.reset_n
);
// Blink LED, to indicate everything is working
reg [25: 0] counter;
reg led_level;
always @(posedge fpga_clk_50 or negedge hps_fpga_reset_n) begin
if (~hps_fpga_reset_n) begin
counter <= 0;
led_level <= 0;
end
else if (counter == 24999999) begin
counter <= 0;
led_level <= ~led_level;
end
else
counter <= counter + 1'b1;
end
assign LED[0] = led_level;
endmodule
vta/hardware/intel/scripts/ip/vta/vta_hw.tcl 0 → 100644
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
# regarding copyright ownership. The ASF licenses this file
# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
# request TCL package from ACDS 16.1
package require -exact qsys 16.1
# module vta
set_module_property DESCRIPTION ""
set_module_property NAME vta
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "VTA Subsystem"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
# file sets
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL IntelShell
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file VTAShell.v VERILOG PATH VTAShell.v TOP_LEVEL_FILE
# connection point clock
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clock clk Input 1
# connection point reset
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
# connection point m_axi_gmem
add_interface m_axi_gmem axi start
set_interface_property m_axi_gmem associatedClock clock
set_interface_property m_axi_gmem associatedReset reset
set_interface_property m_axi_gmem readIssuingCapability 1
set_interface_property m_axi_gmem writeIssuingCapability 1
set_interface_property m_axi_gmem combinedIssuingCapability 1
set_interface_property m_axi_gmem ENABLED true
set_interface_property m_axi_gmem EXPORT_OF ""
set_interface_property m_axi_gmem PORT_NAME_MAP ""
set_interface_property m_axi_gmem CMSIS_SVD_VARIABLES ""
set_interface_property m_axi_gmem SVD_ADDRESS_GROUP ""
add_interface_port m_axi_gmem io_mem_ar_ready arready Input 1
add_interface_port m_axi_gmem io_mem_ar_valid arvalid Output 1
add_interface_port m_axi_gmem io_mem_ar_bits_addr araddr Output 32
add_interface_port m_axi_gmem io_mem_ar_bits_burst arburst Output 2
add_interface_port m_axi_gmem io_mem_ar_bits_cache arcache Output 4
add_interface_port m_axi_gmem io_mem_ar_bits_len arlen Output 4
add_interface_port m_axi_gmem io_mem_ar_bits_lock arlock Output 2
add_interface_port m_axi_gmem io_mem_ar_bits_prot arprot Output 3
add_interface_port m_axi_gmem io_mem_ar_bits_size arsize Output 3
add_interface_port m_axi_gmem io_mem_ar_bits_user aruser Output 5
add_interface_port m_axi_gmem io_mem_ar_bits_id arid Output 1
add_interface_port m_axi_gmem io_mem_r_ready rready Output 1
add_interface_port m_axi_gmem io_mem_r_valid rvalid Input 1
add_interface_port m_axi_gmem io_mem_r_bits_data rdata Input 64
add_interface_port m_axi_gmem io_mem_r_bits_id rid Input 1
add_interface_port m_axi_gmem io_mem_r_bits_last rlast Input 1
add_interface_port m_axi_gmem io_mem_r_bits_resp rresp Input 2
add_interface_port m_axi_gmem io_mem_aw_valid awvalid Output 1
add_interface_port m_axi_gmem io_mem_aw_ready awready Input 1
add_interface_port m_axi_gmem io_mem_aw_bits_addr awaddr Output 32
add_interface_port m_axi_gmem io_mem_aw_bits_prot awprot Output 3
add_interface_port m_axi_gmem io_mem_aw_bits_burst awburst Output 2
add_interface_port m_axi_gmem io_mem_aw_bits_cache awcache Output 4
add_interface_port m_axi_gmem io_mem_aw_bits_len awlen Output 4
add_interface_port m_axi_gmem io_mem_aw_bits_lock awlock Output 2
add_interface_port m_axi_gmem io_mem_aw_bits_size awsize Output 3
add_interface_port m_axi_gmem io_mem_aw_bits_user awuser Output 5
add_interface_port m_axi_gmem io_mem_aw_bits_id awid Output 1
add_interface_port m_axi_gmem io_mem_w_bits_data wdata Output 64
add_interface_port m_axi_gmem io_mem_w_ready wready Input 1
add_interface_port m_axi_gmem io_mem_w_valid wvalid Output 1
add_interface_port m_axi_gmem io_mem_w_bits_last wlast Output 1
add_interface_port m_axi_gmem io_mem_w_bits_strb wstrb Output 8
add_interface_port m_axi_gmem io_mem_w_bits_id wid Output 1
add_interface_port m_axi_gmem io_mem_b_ready bready Output 1
add_interface_port m_axi_gmem io_mem_b_valid bvalid Input 1
add_interface_port m_axi_gmem io_mem_b_bits_resp bresp Input 2
add_interface_port m_axi_gmem io_mem_b_bits_id bid Input 1
# connection point s_axi_control
add_interface s_axi_control axi end
set_interface_property s_axi_control associatedClock clock
set_interface_property s_axi_control associatedReset reset
set_interface_property s_axi_control readAcceptanceCapability 1
set_interface_property s_axi_control writeAcceptanceCapability 1
set_interface_property s_axi_control combinedAcceptanceCapability 1
set_interface_property s_axi_control readDataReorderingDepth 1
set_interface_property s_axi_control bridgesToMaster ""
set_interface_property s_axi_control ENABLED true
set_interface_property s_axi_control EXPORT_OF ""
set_interface_property s_axi_control PORT_NAME_MAP ""
set_interface_property s_axi_control CMSIS_SVD_VARIABLES ""
set_interface_property s_axi_control SVD_ADDRESS_GROUP ""
add_interface_port s_axi_control io_host_aw_ready awready Output 1
add_interface_port s_axi_control io_host_aw_valid awvalid Input 1
add_interface_port s_axi_control io_host_aw_bits_addr awaddr Input 16
add_interface_port s_axi_control io_host_aw_bits_prot awprot Input 3
add_interface_port s_axi_control io_host_w_valid wvalid Input 1
add_interface_port s_axi_control io_host_w_ready wready Output 1
add_interface_port s_axi_control io_host_w_bits_data wdata Input 32
add_interface_port s_axi_control io_host_b_ready bready Input 1
add_interface_port s_axi_control io_host_b_valid bvalid Output 1
add_interface_port s_axi_control io_host_b_bits_resp bresp Output 2
add_interface_port s_axi_control io_host_ar_ready arready Output 1
add_interface_port s_axi_control io_host_ar_valid arvalid Input 1
add_interface_port s_axi_control io_host_ar_bits_addr araddr Input 16
add_interface_port s_axi_control io_host_ar_bits_prot arprot Input 3
add_interface_port s_axi_control io_host_r_ready rready Input 1
add_interface_port s_axi_control io_host_r_valid rvalid Output 1
add_interface_port s_axi_control io_host_r_bits_resp rresp Output 2
add_interface_port s_axi_control io_host_r_bits_data rdata Output 32
add_interface_port s_axi_control io_host_aw_bits_id awid Input 13
add_interface_port s_axi_control io_host_ar_bits_id arid Input 13
add_interface_port s_axi_control io_host_aw_bits_len awlen Input 4
add_interface_port s_axi_control io_host_ar_bits_size arsize Input 3
add_interface_port s_axi_control io_host_r_bits_id rid Output 13
add_interface_port s_axi_control io_host_w_bits_id wid Input 13
add_interface_port s_axi_control io_host_b_bits_id bid Output 13
add_interface_port s_axi_control io_host_aw_bits_size awsize Input 3
add_interface_port s_axi_control io_host_aw_bits_burst awburst Input 2
add_interface_port s_axi_control io_host_aw_bits_lock awlock Input 2
add_interface_port s_axi_control io_host_aw_bits_cache awcache Input 4
add_interface_port s_axi_control io_host_ar_bits_burst arburst Input 2
add_interface_port s_axi_control io_host_ar_bits_cache arcache Input 4
add_interface_port s_axi_control io_host_ar_bits_len arlen Input 4
add_interface_port s_axi_control io_host_ar_bits_lock arlock Input 2
add_interface_port s_axi_control io_host_r_bits_last rlast Output 1
add_interface_port s_axi_control io_host_w_bits_last wlast Input 1
add_interface_port s_axi_control io_host_w_bits_strb wstrb Input 4
vta/hardware/intel/scripts/set_attrs.py 0 → 100755
#!/usr/bin/env python
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
# regarding copyright ownership. The ASF licenses this file
# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
import os, sys
import argparse
def set_attrs(fname, fname_out, dsp=False, verbose=True):
"""Set attributes to precompiled verilog code to indicate synthesis preference.
Parameters
----------
fname : str
The name of input verilog source code file.
fname_out : str
The name of output verilog source code file.
"""
out = ""
with open(fname, 'rt') as fp:
module = ''
for idx, line in enumerate(fp):
if 'module' in line:
module = line[line.find('module')+7:line.find('(')]
out += line
elif " * " in line:
if dsp:
line = line.replace(" * ", ' * (* multstyle="dsp" *) ')
else:
line = line.replace(" * ", ' * (* multstyle="logic" *) ')
if verbose:
print(fname_out+":"+str(idx+1)+": "+module+":"+line[1:line.find(";")+1])
out += line
elif "rA;" in line:
line = line.replace("rA;", 'rA /* synthesis noprune */;')
if verbose:
print(fname_out+":"+str(idx+1)+": "+module+":"+line[1:line.find(";")+1])
out += line
elif "rB;" in line:
line = line.replace("rB;", 'rB /* synthesis noprune */;')
if verbose:
print(fname_out+":"+str(idx+1)+": "+module+":"+line[1:line.find(";")+1])
out += line
elif "rC;" in line:
line = line.replace("rC;", 'rC /* synthesis noprune */;')
if verbose:
print(fname_out+":"+str(idx+1)+": "+module+":"+line[1:line.find(";")+1])
out += line
else:
out += line
with open(fname_out, 'wt') as fp:
fp.write(out)
if __name__=="__main__":
parser = argparse.ArgumentParser(description='Set attributes to precompiled ' +
'verilog code to indicate synthesis preference')
parser.add_argument('-i', '--input', type=str, default='VTA.DefaultDe10Config.v',
help='input verilog file to be decorated')
parser.add_argument('-o', '--output', type=str, default='IntelShell.v',
help='decorated verilog file')
parser.add_argument('--dsp', default=False, action='store_true',
help='use dsp instead of logic.')
parser.add_argument('--verbose', default=False, action='store_true',
help='print output file name and decorated lines.')
args = parser.parse_args()
set_attrs(args.input, args.output, args.dsp, args.verbose)
vta/hardware/intel/scripts/set_clocks.sdc 0 → 100644
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
# regarding copyright ownership. The ASF licenses this file
# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
#**************************************************************
# This .sdc file is created by Terasic Tool.
# Users are recommended to modify this file to match users logic.
#**************************************************************
# Create Clock
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
# for enhancing USB BlasterII to be reliable, 25MHz
create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
# Create Generated Clock
derive_pll_clocks
# Set Clock Uncertainty
derive_clock_uncertainty
vta/hardware/intel/scripts/soc_system.tcl 0 → 100644
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
# regarding copyright ownership. The ASF licenses this file
# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
package require -exact qsys 16.0
create_system soc_system
set_project_property DEVICE [lindex $argv 0]
set_project_property DEVICE_FAMILY [lindex $argv 1]
# module properties
set_module_property NAME soc_system
# Instances and instance parameters
# (disabled instances are intentionally culled)
add_instance clk_0 clock_source 18.1
set_instance_parameter_value clk_0 {clockFrequency} {50000000.0}
set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}
add_instance hps_0 altera_hps 18.1
set_instance_parameter_value hps_0 {HPS_PROTOCOL} {DDR3}
set_instance_parameter_value hps_0 {MEM_ASR} {Manual}
set_instance_parameter_value hps_0 {MEM_ATCL} {Disabled}
set_instance_parameter_value hps_0 {MEM_AUTO_LEVELING_MODE} {1}
set_instance_parameter_value hps_0 {MEM_BANKADDR_WIDTH} {3}
set_instance_parameter_value hps_0 {MEM_BL} {OTF}
set_instance_parameter_value hps_0 {MEM_BT} {Sequential}
set_instance_parameter_value hps_0 {MEM_CK_PHASE} {0.0}
set_instance_parameter_value hps_0 {MEM_CK_WIDTH} {1}
set_instance_parameter_value hps_0 {MEM_CLK_EN_WIDTH} {1}
set_instance_parameter_value hps_0 {MEM_CLK_FREQ} {400.0}
set_instance_parameter_value hps_0 {MEM_CLK_FREQ_MAX} {800.0}
set_instance_parameter_value hps_0 {MEM_COL_ADDR_WIDTH} {10}
set_instance_parameter_value hps_0 {MEM_CS_WIDTH} {1}
set_instance_parameter_value hps_0 {MEM_DEVICE} {MISSING_MODEL}
set_instance_parameter_value hps_0 {MEM_DLL_EN} {1}
set_instance_parameter_value hps_0 {MEM_DQ_PER_DQS} {8}
set_instance_parameter_value hps_0 {MEM_DQ_WIDTH} {32}
set_instance_parameter_value hps_0 {MEM_DRV_STR} {RZQ/6}
set_instance_parameter_value hps_0 {MEM_FORMAT} {DISCRETE}
set_instance_parameter_value hps_0 {MEM_GUARANTEED_WRITE_INIT} {0}
set_instance_parameter_value hps_0 {MEM_IF_BOARD_BASE_DELAY} {10}
set_instance_parameter_value hps_0 {MEM_IF_DM_PINS_EN} {1}
set_instance_parameter_value hps_0 {MEM_IF_DQSN_EN} {1}
set_instance_parameter_value hps_0 {MEM_IF_SIM_VALID_WINDOW} {0}
set_instance_parameter_value hps_0 {MEM_INIT_EN} {0}
set_instance_parameter_value hps_0 {MEM_INIT_FILE} {}
set_instance_parameter_value hps_0 {MEM_MIRROR_ADDRESSING} {0}
set_instance_parameter_value hps_0 {MEM_NUMBER_OF_DIMMS} {1}
set_instance_parameter_value hps_0 {MEM_NUMBER_OF_RANKS_PER_DEVICE} {1}
set_instance_parameter_value hps_0 {MEM_NUMBER_OF_RANKS_PER_DIMM} {1}
set_instance_parameter_value hps_0 {MEM_PD} {DLL off}
set_instance_parameter_value hps_0 {MEM_RANK_MULTIPLICATION_FACTOR} {1}
set_instance_parameter_value hps_0 {MEM_ROW_ADDR_WIDTH} {15}
set_instance_parameter_value hps_0 {MEM_RTT_NOM} {RZQ/6}
set_instance_parameter_value hps_0 {MEM_RTT_WR} {Dynamic ODT off}
set_instance_parameter_value hps_0 {MEM_SRT} {Normal}
set_instance_parameter_value hps_0 {MEM_TCL} {7}
set_instance_parameter_value hps_0 {MEM_TFAW_NS} {37.5}
set_instance_parameter_value hps_0 {MEM_TINIT_US} {500}
set_instance_parameter_value hps_0 {MEM_TMRD_CK} {4}
set_instance_parameter_value hps_0 {MEM_TRAS_NS} {35.0}
set_instance_parameter_value hps_0 {MEM_TRCD_NS} {13.75}
set_instance_parameter_value hps_0 {MEM_TREFI_US} {7.8}
set_instance_parameter_value hps_0 {MEM_TRFC_NS} {300.0}
set_instance_parameter_value hps_0 {MEM_TRP_NS} {13.75}
set_instance_parameter_value hps_0 {MEM_TRRD_NS} {7.5}
set_instance_parameter_value hps_0 {MEM_TRTP_NS} {7.5}
set_instance_parameter_value hps_0 {MEM_TWR_NS} {15.0}
set_instance_parameter_value hps_0 {MEM_TWTR} {4}
set_instance_parameter_value hps_0 {MEM_USER_LEVELING_MODE} {Leveling}
set_instance_parameter_value hps_0 {MEM_VENDOR} {Other}
set_instance_parameter_value hps_0 {MEM_VERBOSE} {1}
set_instance_parameter_value hps_0 {MEM_VOLTAGE} {1.5V DDR3}
set_instance_parameter_value hps_0 {MEM_WTCL} {7}
set_instance_parameter_value hps_0 {F2SCLK_COLDRST_Enable} {0}
set_instance_parameter_value hps_0 {F2SCLK_DBGRST_Enable} {0}
set_instance_parameter_value hps_0 {F2SCLK_PERIPHCLK_Enable} {0}
set_instance_parameter_value hps_0 {F2SCLK_SDRAMCLK_Enable} {0}
set_instance_parameter_value hps_0 {F2SCLK_WARMRST_Enable} {0}
set_instance_parameter_value hps_0 {LWH2F_Enable} {true}
set_instance_parameter_value hps_0 {S2F_Width} {0}
set_instance_parameter_value hps_0 {F2SDRAM_Type} {}
set_instance_parameter_value hps_0 {F2SDRAM_Width} {}
set_instance_parameter_value hps_0 {MPU_EVENTS_Enable} {0}
add_instance vta_0 vta 1.0
# connections and connection parameters
add_connection clk_0.clk hps_0.f2h_axi_clock clock
add_connection clk_0.clk hps_0.h2f_lw_axi_clock clock
add_connection clk_0.clk vta_0.clock clock
add_connection clk_0.clk_reset vta_0.reset reset
add_connection hps_0.h2f_lw_axi_master vta_0.s_axi_control avalon
set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control arbitrationPriority {1}
set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control baseAddress {0x00020000}
set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control defaultConnection {0}
add_connection vta_0.m_axi_gmem hps_0.f2h_axi_slave avalon
set_connection_parameter_value vta_0.m_axi_gmem/hps_0.f2h_axi_slave arbitrationPriority {1}
set_connection_parameter_value vta_0.m_axi_gmem/hps_0.f2h_axi_slave baseAddress {0x0000}
set_connection_parameter_value vta_0.m_axi_gmem/hps_0.f2h_axi_slave defaultConnection {0}
# exported interfaces
add_interface clk clock sink
set_interface_property clk EXPORT_OF clk_0.clk_in
add_interface hps_0_h2f_reset reset source
set_interface_property hps_0_h2f_reset EXPORT_OF hps_0.h2f_reset
add_interface memory conduit end
set_interface_property memory EXPORT_OF hps_0.memory
add_interface reset reset sink
set_interface_property reset EXPORT_OF clk_0.clk_in_reset
# interconnect requirements
set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {HANDSHAKE}
set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {1}
save_system soc_system.qsys
vta/python/vta/pkg_config.py
......@@ -109,7 +109,24 @@ class PkgConfig(object):
# - axi_cache_bits: ARCACHE/AWCACHE signals for the AXI bus
# (e.g. 1111 is write-back read and write allocate)
# - axi_prot_bits: ARPROT/AWPROT signals for the AXI bus
if self.TARGET == "ultra96":
if self.TARGET == "de10nano":
self.fpga_device = "5CSEBA6U23I7"
self.fpga_family = "Cyclone\\ V"
# TODO: The following parameters have not been propagated into
# current Chisel-based implement of VTA hardware for DE10-Nano.
# A future change should be made to propagate these parameters,
# in order to avoid duplicated definition.
self.fpga_freq = 100
self.fpga_per = 2
self.fpga_log_axi_bus_width = 6
self.axi_prot_bits = '100'
# IP register address map
self.ip_reg_map_range = "0x1000"
self.fetch_base_addr = "0xFF220000"
self.load_base_addr = "0xFF221000"
self.compute_base_addr = "0xFF222000"
self.store_base_addr = "0xFF223000"
elif self.TARGET == "ultra96":
self.fpga_device = "xczu3eg-sbva484-1-e"
self.fpga_family = "zynq-ultrascale+"
self.fpga_freq = 333
......
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