- 17 Jan, 2020 1 commit
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* Update task_python_vta.sh * install sbt=1.1.1 with apt-get * update verilator_opt * install verilator with major version 4.0 * disable multi-threading for now * bug fix for correcting uop fetch address in LoadUop module * bug fix for correcting uop fetch address in LoadUop module * adjustment to read from dram_offset * enable USE_THREADS with verilator 4.x * DEBUG: try avoid core dump with verilator 4.x * bug fix in LoadUop module * log mega cycles in tsim * download cat.png to avoid fetching in each run * bug fix in LoadUop module * solve dram_even/sram_even issue * bug fix * introduce scalalint in ci * speedup tsim in ci * bug fix * lint scala code before building * disable multi-threading * split fsim/tsim script * update Jenkins settings * duplicate task_python_vta_fsim.sh as task_python_vta.sh for now Co-authored-by: Thierry Moreau <tmoreau@octoml.ai>
Liangfu Chen committed
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- 14 Jan, 2020 1 commit
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Liangfu Chen committed
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- 06 Jan, 2020 1 commit
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Kevin Yuan committed
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- 23 Dec, 2019 1 commit
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* [VTA][Chisel] End-to-end Inference with Chisel VTA * Update TensorAlu.scala
Liangfu Chen committed
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- 28 Nov, 2019 1 commit
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Liangfu Chen committed
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- 27 Nov, 2019 1 commit
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* disable pipelined adder and enable streamlined gemm execution * pipeline first layer of adder * explain difference between pipeadder and adder * add comment for explaining the hard-coded latency
Liangfu Chen committed
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- 15 Nov, 2019 1 commit
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* bug fix for padded load with large inputs * Update TensorLoad.scala * Update test_vta_insn.py
Liangfu Chen committed
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- 06 Nov, 2019 1 commit
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* Update TensorUtil.scala * Update test_vta_insn.py
Liangfu Chen committed
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- 04 Sep, 2019 2 commits
- 27 Aug, 2019 1 commit
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Liangfu Chen committed
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- 14 Aug, 2019 1 commit
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* [VTA][Chisel] scale dram base address in hardware instead of runtime * remove trailing spaces
Luis Vega committed
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- 13 Aug, 2019 1 commit
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* added alutest * fix indent * name change for cycle * improved data gen and infra * added alutest * fix indent * name change for cycle * improved data gen and infra * fix space * fix indent * fixes * aluRef * fix randomarary * add * Revert "add" This reverts commit 87077daebbe055dee11f80e37da3a6291138e0f0. * Revert "fix randomarary" This reverts commit df386c1e660eb6ebcff1a1f905610573676f1589. * Revert "aluRef" This reverts commit 8665f0d4a7b12b796b2cb1ca6bf9cfe5613ee389. * should fix dlmc-core
Benjamin Tu committed
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- 08 Aug, 2019 1 commit
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* fix * fixes
Benjamin Tu committed
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- 31 Jul, 2019 1 commit
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* initial compilation script for chisel-vta; * replace tabs with spaces; * compile script for de10-nano; * remove generated verilog source code; * remove `altsource_probe`, `debounce`, `edge_detect` ip; * replace quartus project files with a single tcl script; * Update install.md * improved makefile-based compilation script; * complete makefile-based compilation of chisel-vta for de10-nano; * install quartus; * conversion to .rbf file; * document chisel-vta compilation process for de10-nano; * rename generated bitstream file; * download and extract custom ip for de10-nano; * minor change * minor change * fix indentation; * bug fix; * improved robustness in makefile; * clean up; * add `.sdc .ipx .qsys` allowance in jenkins; * add ASF header; * add ASF header; * remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys; * add ASF header; * keep sources compact; * keep sources compact; * it's not necessary now * AXI4LiteClient -> AXI3Client for IntelShell * remove connection to fpga_only_master; * a few important bug fix: wire reset pin, and set host_r_last to high * remove intel specific interface definition; * add NO_DSP option in Makefile; * AXI4Lite is not used in IntelShell; * minor fix: disable dsp and use logic instead; * quartus version change: 18.0 -> 18.1 * remove altera related statement; * compose compile_design.tcl * initial tcl script for soc_system generation; * remove .qsys file; * remove unused; * .qsys can be generated by tcl script; * remove hps_io and shrink size of soc_system; * integrate into makefile; * version change: 18.0 -> 18.1 * add sample config file for de10-nano; * parameterize DEVICE and PROJECT_NAME * remove extra lines; * brief description on flashing sd card image for de10-nano * docs on building additional components * parameterize DEVICE and DEVICE_FAMILY * parameterize DEVICE and DEVICE_FAMILY * parameterize DEVICE and DEVICE_FAMILY * de10-nano -> de10nano * minor change * add comment in code and document in order to address review comments;
Liangfu Chen committed
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- 29 Jul, 2019 1 commit
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Luis Vega committed
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- 28 Jul, 2019 2 commits
- 27 Jul, 2019 1 commit
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* fix tensor issue/commit in gemm * remove trailing spaces
Luis Vega committed
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- 26 Jul, 2019 1 commit
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* support for different inp/wgt bits, rewrote dot for clarity * [VTA] [Chisel] support for different inp/wgt bits, rewrote DotProduct for clarity * [VTA] [Chisel] support for different inp/wgt bits, rewrote DotProduct for clarity * change back to sim * fix index * fix index * fix indent * fix indent * fix indent * fix trailing spaces * fix trailing spaces * change to more descriptive name * matric->matrix * fix spacing * fix spacing & added generic name for dot * better parameter flow * spacing * spacing * spacing * update requirement (tested) for dot, spacing * function call convention * small edit
Benjamin Tu committed
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- 23 Jul, 2019 1 commit
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Luis Vega committed
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- 21 Jul, 2019 1 commit
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Luis Vega committed
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- 17 Jul, 2019 1 commit
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Luis Vega committed
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- 08 Jul, 2019 1 commit
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* add tsim init function * add sim device * test wait and resume * launch simulation thread from DPILoader * add VTASimDPI module to handle all simulation related stuff * test tsim init * move exit to simdpi module * update vta driver * add chisel DPI module * get back simshell * update vta to support dpi sim * update unittests * add tsim to integration-conv2d test * run resnet on tsim * remove max-cycles * match tsim counters with sim counters * use env in simulator to switch between sim and tsim * update unittest * rollback conv2d test * update resnet * add stats to matrix multiply * add stats * print stats after assert * update other tests * add stats to gemm * add return and remove unused libs * add missing arg * return lib * update comments for linter * add more comments to VTASimDPI module * remove trailing spaces * remove trailing spaces
Luis Vega committed
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- 13 Jun, 2019 1 commit
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* add support to event counters in VTA * fix comment * fix event-counter interface parameter * no longer needed * add sim back * add docs to event counters * fix docs * add more details about event counting * make dpi-module docs more accurate
Luis Vega committed
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- 05 Jun, 2019 1 commit
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Luis Vega committed
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- 08 May, 2019 1 commit
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* merge files * move verilator to the right place * change name to tsim * add default rule to be build and run * add README for tsim * Update README.md * add some structural feedback * change name of VTASim to VTADPISim * more renaming * update comment * add license * fix indentation * add switch for vta-tsim * add more licenses * update readme * address some of the new feedback * add some feedback from cpplint * add one more whitespace * pass pointer so linter is happy * pass pointer so linter is happy * README moved to vta documentation * create types for dpi functions, so they can be handle easily * fix pointer style * add feedback from docs * parametrize width data and pointers * fix comments * fix comment * add comment to class * add missing parameters * move README back to tsim example * add feedback * add more comments and remove un-necessary argument in finish * update comments * fix cpplint * fix doc
Luis Vega committed
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