- 12 Oct, 2019 1 commit
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- Fix abc_model.v to abc9_model.v in techlibs paths; - synth_xilinx. Add tests for new options; - synth_ecp5. Add tests for new options; - Expand coverage for synth_dsp command;
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- 07 Oct, 2019 1 commit
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- 30 Sep, 2019 1 commit
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Divided to understand regress on #171 build.
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- 10 Sep, 2019 2 commits
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-ice40_wrapcarry -test_pmgen -xilinx_srl
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- 09 Sep, 2019 2 commits
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- 09 Aug, 2019 1 commit
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- 07 Aug, 2019 1 commit
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SergeyDegtyar committed
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- 29 Jul, 2019 1 commit
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Miodrag Milanovic committed
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- 15 Jul, 2019 1 commit
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Eddie Hung committed
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- 26 Jun, 2019 1 commit
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Miodrag Milanovic committed
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- 24 Jun, 2019 1 commit
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SergeyDegtyar committed
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- 28 May, 2019 1 commit
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Add tests for commits: - Add "wreduce -keepdc"; - Add "fmcombine -initeq -anyeq"; - Add "stat -tech xilinx"; - Add "synth_xilinx -arch".
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- 03 May, 2019 1 commit
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Miodrag Milanovic committed
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- 26 Apr, 2019 1 commit
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Miodrag Milanovic committed
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- 11 Apr, 2019 1 commit
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Eddie Hung committed
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- 10 Apr, 2019 1 commit
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Add new tests to backends and architecture; Merge commit "Add regression test for Yosys PR 896"
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- 03 Apr, 2019 1 commit
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SergeyDegtyar committed
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- 28 Feb, 2019 1 commit
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Eddie Hung committed
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- 27 Jan, 2019 1 commit
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Miodrag Milanovic committed
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- 24 Jan, 2019 1 commit
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1. Add tests for synth_anlogic command Now this tests are commented because of: + iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v ../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to bind wire/reg/memory `A' in `testbench.uut._09_' ../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to elaborate r-value: (INIT)>>(A) 2 error(s) during elaboration. 2. Add 'regression' test
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- 15 Jan, 2019 1 commit
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