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lvzhengyang
yosys-tests
Commits
1d599939
Commit
1d599939
authored
Aug 09, 2019
by
SergeyDegtyar
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Fix regressions (build #110): opt_lut removed.
parent
4332e325
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7 changed files
with
1 additions
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10 deletions
+1
-10
architecture/Makefile
+1
-1
architecture/scripts/synth_ice40_abc9.ys
+0
-1
architecture/scripts/synth_ice40_unlut.ys
+0
-4
simple/scripts/opt_lut.ys
+0
-1
simple/scripts/opt_lut_dlogic.ys
+0
-1
simple/scripts/opt_lut_limit.ys
+0
-1
simple/scripts/opt_lut_limit_0.ys
+0
-1
No files found.
architecture/Makefile
View file @
1d599939
...
...
@@ -49,7 +49,7 @@ $(eval $(call template,synth_gowin_error,synth_gowin_fully_selected ))
#ice40
$(eval
$(call
template,synth_ice40,synth_ice40
synth_ice40_top
synth_ice40_blif
synth_ice40_edif
synth_ice40_json
synth_ice40_run
synth_ice40_noflatten
synth_ice40_flatten
synth_ice40_retime
synth_ice40_nocarry
synth_ice40_nodffe
synth_ice40_nobram
synth_ice40_abc2
synth_ice40_vpr
synth_ice40_relut
synth_ice40_dsp
synth_ice40_min_ce
synth_ice40_noabc
synth_ice40_device_u
synth_ice40_device_lp
synth_ice40_device_hx
synth_ice40_opt))
$(eval
$(call
template,synth_ice40_mem,synth_ice40
synth_ice40_top
synth_ice40_blif
synth_ice40_edif
synth_ice40_json
synth_ice40_run
synth_ice40_noflatten
synth_ice40_flatten
synth_ice40_retime
synth_ice40_nocarry
synth_ice40_nodffe
synth_ice40_nobram
synth_ice40_abc2
synth_ice40_vpr
synth_ice40_relut
synth_ice40_dsp
synth_ice40_min_ce
synth_ice40_noabc
synth_ice40_device_u
synth_ice40_device_lp
synth_ice40_device_hx
synth_ice40_abc9
synth_ice40_unlut
synth_ice40_opt))
$(eval
$(call
template,synth_ice40_mem,synth_ice40
synth_ice40_top
synth_ice40_blif
synth_ice40_edif
synth_ice40_json
synth_ice40_run
synth_ice40_noflatten
synth_ice40_flatten
synth_ice40_retime
synth_ice40_nocarry
synth_ice40_nodffe
synth_ice40_nobram
synth_ice40_abc2
synth_ice40_vpr
synth_ice40_relut
synth_ice40_dsp
synth_ice40_min_ce
synth_ice40_noabc
synth_ice40_device_u
synth_ice40_device_lp
synth_ice40_device_hx
synth_ice40_abc9
synth_ice40_opt))
$(eval
$(call
template,synth_ice40_wide_ffs,synth_ice40
synth_ice40_top
synth_ice40_blif
synth_ice40_edif
synth_ice40_json
synth_ice40_run
synth_ice40_noflatten
synth_ice40_flatten
synth_ice40_nocarry
synth_ice40_nodffe
synth_ice40_nobram
synth_ice40_abc2
synth_ice40_vpr
synth_ice40_relut
synth_ice40_dsp
synth_ice40_min_ce
synth_ice40_noabc
synth_ice40_device_u
synth_ice40_device_lp
synth_ice40_device_hx
synth_ice40_opt))
$(eval
$(call
template,synth_ice40_fulladder,synth_ice40
synth_ice40_top
synth_ice40_blif
synth_ice40_edif
synth_ice40_json
synth_ice40_run
synth_ice40_noflatten
synth_ice40_flatten
synth_ice40_nocarry
synth_ice40_nodffe
synth_ice40_nobram
synth_ice40_abc2
synth_ice40_vpr
synth_ice40_relut
synth_ice40_dsp
synth_ice40_min_ce
synth_ice40_noabc
synth_ice40_device_u
synth_ice40_device_lp
synth_ice40_device_hx
synth_ice40_opt))
$(eval
$(call
template,synth_ice40_error,synth_ice40_fully_selected
synth_ice40_abc9_retime
synth_ice40_device_unknown))
...
...
architecture/scripts/synth_ice40_abc9.ys
View file @
1d599939
read_verilog ../top.v
synth_ice40 -abc9
ice40_unlut
ice40_opt
write_verilog synth.v
architecture/scripts/synth_ice40_unlut.ys
deleted
100644 → 0
View file @
4332e325
read_verilog ../top.v
synth_ice40
ice40_unlut
write_verilog synth.v
simple/scripts/opt_lut.ys
View file @
1d599939
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut
design -reset
read_verilog ../top.v
...
...
simple/scripts/opt_lut_dlogic.ys
View file @
1d599939
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut -dlogic $_ANDNOT_:A=I0
design -reset
read_verilog ../top.v
...
...
simple/scripts/opt_lut_limit.ys
View file @
1d599939
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut -limit 2
design -reset
read_verilog ../top.v
...
...
simple/scripts/opt_lut_limit_0.ys
View file @
1d599939
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut -limit 0
design -reset
read_verilog ../top.v
...
...
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