Add new tests to 'architecture' test group

architecture/Makefile

@@ -38,20 +38,21 @@ $(eval $(call template,synth_coolrunner2_error,synth_coolrunner2_fully_selected)
 $(eval $(call template,synth_easic_error,synth_easic_fully_selected))
 
 #ecp5
-$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
-$(eval $(call template,synth_ecp5_wide_ffs,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
+$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit synth_ecp5_abc9 synth_ecp5_abc9_nowidelut))
+$(eval $(call template,synth_ecp5_wide_ffs,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit  synth_ecp5_abc9 synth_ecp5_abc9_nowidelut))
 $(eval $(call template,synth_ecp5_error,synth_ecp5_fully_selected))
 
 #gowin
-$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten ))
-$(eval $(call template,synth_gowin_mem,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten ))
+$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe ))
+$(eval $(call template,synth_gowin_mem,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe ))
 $(eval $(call template,synth_gowin_error,synth_gowin_fully_selected ))
 
 #ice40
-$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
-$(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
-$(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
-$(eval $(call template,synth_ice40_error,synth_ice40_fully_selected))
+$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
+$(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_abc9 synth_ice40_unlut synth_ice40_opt))
+$(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
+$(eval $(call template,synth_ice40_fulladder,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
+$(eval $(call template,synth_ice40_error,synth_ice40_fully_selected synth_ice40_abc9_retime synth_ice40_device_unknown))
 
 #intel
 $(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_iopads synth_intel_nobram synth_intel_max10 ))
@@ -67,8 +68,8 @@ $(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf
 $(eval $(call template,synth_sf2_error,synth_sf2_fully_selected ))
 
 #xilinx
-$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl))
-$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch ))
+$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl synth_xilinx_widemux synth_xilinx_nowidelut synth_xilinx_nocarry synth_xilinx_arch_xc6s_abc9 synth_xilinx_widemux_9 synth_xilinx_widemux_2 synth_xilinx_widemux_3 synth_xilinx_nowidelut_abc9))
+$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch synth_xilinx_abc9_retime synth_xilinx_widemux_1))
 ifeq ($(ENABLE_HEAVY_TESTS),1)
 $(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
 $(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
@@ -77,6 +78,7 @@ endif
 #greenpak4
 $(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
 $(eval $(call template,synth_greenpak4_wide_ffs,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
+$(eval $(call template,synth_greenpak4_dffs_r,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
 $(eval $(call template,synth_greenpak4_error,synth_greenpak4_fully_selected synth_greenpak4_invalid_part))
 
 .PHONY: all clean

architecture/run.sh

@@ -22,6 +22,14 @@ if echo "$1" | grep ".*_error"; then
 		expected_string="ERROR: Invalid or no family specified:"
 	elif [ "$2" = "synth_xilinx_invalid_arch" ]; then
 		expected_string="ERROR: Invalid Xilinx -family setting: "
+	elif [ "$2" = "synth_xilinx_widemux_1" ]; then
+		expected_string="ERROR: -widemux value must be 0 or >= 2."
+	elif [ "$2" = "synth_xilinx_abc9_retime" ]; then
+		expected_string="ERROR: -retime option not currently compatible with -abc9!"
+	elif [ "$2" = "synth_ice40_abc9_retime" ]; then
+		expected_string="ERROR: -retime option not currently compatible with -abc9!"
+	elif [ "$2" = "synth_ice40_device_unknown" ]; then
+		expected_string="ERROR: Invalid or no device specified: "
 	fi
 
 	if yosys -ql yosys.log ../../scripts/$2.ys; then
@@ -87,6 +95,8 @@ else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 	elif [ "$1" = "synth_ice40_wide_ffs" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
+	elif [ "$1" = "synth_ice40_fulladder" ]; then
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 	elif [ "$1" = "synth_intel" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
 	elif [ "$1" = "synth_intel_a10gx" ]; then
@@ -107,6 +117,8 @@ else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
 	elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
+	elif [ "$1" = "synth_greenpak4_dffs_r" ]; then
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
 	else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v
 	fi

architecture/scripts/synth_ecp5_abc9.ys

+read_verilog ../top.v
+synth_ecp5 -abc9
+write_verilog synth.v

architecture/scripts/synth_ecp5_abc9_nowidelut.ys

+read_verilog ../top.v
+synth_ecp5 -abc9 -nowidelut
+write_verilog synth.v

architecture/scripts/synth_gowin_nodffe.ys

+read_verilog ../top.v
+synth_gowin -nodffe
+write_verilog synth.v

architecture/scripts/synth_gowin_nodram.ys

+read_verilog ../top.v
+synth_gowin -nodram
+write_verilog synth.v

architecture/scripts/synth_ice40_abc9.ys

+read_verilog ../top.v
+synth_ice40 -abc9
+ice40_unlut
+ice40_opt
+write_verilog synth.v

architecture/scripts/synth_ice40_abc9_retime.ys

+read_verilog ../top.v
+synth_ice40 -abc9 -retime
+write_verilog synth.v

architecture/scripts/synth_ice40_device_hx.ys

+read_verilog ../top.v
+synth_ice40 -device hx
+write_verilog synth.v

architecture/scripts/synth_ice40_device_lp.ys

+read_verilog ../top.v
+synth_ice40 -device lp
+write_verilog synth.v

architecture/scripts/synth_ice40_device_u.ys

+read_verilog ../top.v
+synth_ice40 -device u
+write_verilog synth.v

architecture/scripts/synth_ice40_device_unknown.ys

+read_verilog ../top.v
+synth_ice40 -device unknown
+write_verilog synth.v

architecture/scripts/synth_ice40_opt.ys

+read_verilog ../top.v
+synth_ice40
+ice40_opt
+write_verilog synth.v

architecture/scripts/synth_ice40_unlut.ys

+read_verilog ../top.v
+synth_ice40
+ice40_unlut
+write_verilog synth.v

architecture/scripts/synth_xilinx_abc9.ys

+read_verilog ../top.v
+synth_xilinx -abc9
+write_verilog synth.v

architecture/scripts/synth_xilinx_abc9_retime.ys

+read_verilog ../top.v
+synth_xilinx -abc9 -retime
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xc6s_abc9.ys

+read_verilog ../top.v
+synth_xilinx -arch xc6s -abc9
+write_verilog synth.v

architecture/scripts/synth_xilinx_nocarry.ys

+read_verilog ../top.v
+synth_xilinx -nocarry
+write_verilog synth.v

architecture/scripts/synth_xilinx_nowidelut.ys

+read_verilog ../top.v
+synth_xilinx -nowidelut
+write_verilog synth.v

architecture/scripts/synth_xilinx_nowidelut_abc9.ys

+read_verilog ../top.v
+synth_xilinx -nowidelut -abc9
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux.ys

+read_verilog ../top.v
+synth_xilinx -widemux 5
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux_1.ys

+read_verilog ../top.v
+synth_xilinx -widemux 1
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux_2.ys

+read_verilog ../top.v
+synth_xilinx -widemux 2
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux_3.ys

+read_verilog ../top.v
+synth_xilinx -widemux 3
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux_9.ys

+read_verilog ../top.v
+synth_xilinx -widemux 9
+write_verilog synth.v

architecture/synth_greenpak4_dffs_r/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1;
+	reg dffs,dffr = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk, negedge dinA[1] )
+		if ( !dinA[1] )
+			dffs <= 1'b1;
+		else
+            dffs <= dinA[0];
+
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			dffr <= 1'b0;
+		else
+            dffr <= dinA[0];
+
+	assert_dff dffs_test(.clk(clk), .test(doutB), .pat(dffs));
+    assert_dff dffr_test(.clk(clk), .test(doutB1), .pat(dffr));
+
+endmodule

architecture/synth_greenpak4_dffs_r/top.v

+module dffs
+    ( input d, clk, pre, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge pre )
+		if ( !pre )
+`ifndef BUG
+			q <= 1'b1;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffr
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1
+);
+
+dffs u_dffs (
+        .clk (clk ),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+dffr u_dffr (
+        .clk (clk ),
+        .clr (clr ),
+        .d (a ),
+        .q (b1 )
+    );
+
+endmodule

architecture/synth_ice40_fulladder/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_ice40_fulladder/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule