I'm opting for iverilog's interpretation of the specifications here. The
commercial simulators I tested seem to agree.

Co-authored-by: qcorradi <q.corradi22@imperial.ac.uk>
Co-authored-by: Zachary Snow <zach@zachjs.com>

* Remove unneeded begin/end when the loop is a do/while
* Dangling else check passes through statement attributes (bug fix)
* Dangling else check passes through most control flow structures to reduce unneeded begin/end
* Add test case and update changelog

---------

Co-authored-by: qcorradi <q.corradi22@imperial.ac.uk>
Co-authored-by: Zachary Snow <zach@zachjs.com>

- event expressions use Expr over LHS
- stricter AST representation of event controls
- property specs use event expressions directly

- use iverilog's -gstrict-expr-width throughout test suite
- add warnings for excess bits or padding zeroes in number literals
- add new --oversized-numbers parameter to retain support for unsized
  numbers wider than 32 bits
- localized use of oversized numbers to new truncate test suite which
  verifies the behavior of both modes, and compares against the known
  behavior of iverilog

- detect and forbid non-positive size casts
- detect and forbid negative struct pattern literal indices
- avoid invalid constant folding of negative based literals

- updated representation and added codegen for sequence match items
- fix incorrect codegen for `iff` property expression

- convert loops with no or many incrementations
- restrict AST node to only contain traditional initializations
- parser elaborates for loop decls into a synthetic block
- decl list codegen is now specific to parameter decl lists
- update jump conversion special cases for new representation
- first experiments with bimapM

- standardize number casting
- fix extension of casts of unsized literals to 32 bits

In places where an optional space was previously allowed, allow any
number of arbitrary whitespace characters, in line with the spec and
other tools.

- remove outdated flexible partial type eq and show instances
- properly disallow incomplete declarations
- disallow var after net type
- remove unused edge case in InterfaceT representation

- support for additional assignment statements in loop initializations
- greatly improved error messaging in these contexts
- decl parser takes in the ending token; significant related refactoring
- pass through elaboration system tasks
- removed non-blocking assignment operator precedence hack
- preliminary nosim test suite for features unsupported by iverilog

- new net decl to replace net pseudo-type
- support nets with complex base types, including typenames
- support var declaration type prefix for all data types
- support var as lone type shorthand
- refactor AST representation of strengths
- traversal helpers for treating nets as variables
- use decl traversals where appropriate

- automatic pass-through test suite coverage
- fix codegen for interface based typedefs
- allow declaration of generic interface ports in module body
- fix codegen for comments within for loop initialization
- fix codegen of class param decls

- pattern keys now represented as TypeOrExpr
- support for simple integer struct pattern keys