Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
c840bcd6
Commit
c840bcd6
authored
Dec 24, 2022
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
prefer larger base when concatenating numbers
parent
96a108de
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 additions
and
1 deletions
+1
-1
src/Language/SystemVerilog/AST/Number.hs
+1
-1
No files found.
src/Language/SystemVerilog/AST/Number.hs
View file @
c840bcd6
...
...
@@ -454,7 +454,7 @@ instance Semigroup Number where
where
size
=
size1
+
size2
signed
=
False
base
=
selectBase
(
m
in
base1
base2
)
values
kinds
base
=
selectBase
(
m
ax
base1
base2
)
values
kinds
trim
=
flip
mod
.
(
2
^
)
values
=
trim
size2
values2
+
shiftL
(
trim
size1
values1
)
size2
kinds
=
trim
size2
kinds2
+
shiftL
(
trim
size1
kinds1
)
size2
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment