The GCN VCC register has 64 CC values in one registers, one bit for each
vector lane.

Previously we avoided problems with invalid optimizations by not declaring
a mode for the comparison operators, but it turns out that causes other
problems (and build warnings).

Instead, the optimization issues can be avoided by setting
STORE_REGISTER_VALUE to -1, meaning that all the bits are significant.

(It would be better if we could set STORE_REGISTER_VALUE according to the
known mask or vector size, but we can't.)

2020-03-18  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
	(vec_cmp<mode>di_dup): Likewise.
	* config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.

2020-03-18  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (COND_MODE): Delete.
	(COND_INT_MODE): Delete.
	(cond_op): Add "mult".
	(cond_<expander><mode>): Use VEC_ALLREG_MODE.
	(cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.

This patch implements Jason's suggestion of pushing a lambda scope
when parsing a global variable initializer.  That bit worked fine, but
happened to cause g++.dg/opt/dump1.C to not give any
used-but-not-defined warnings.

The reason was no_linkage_check, which considers any lambda that has
an extra-scope to have linkage.  Which is technically correct.  Except
that we think that all types that have linkage have external linkage.

Our representation of linkage and visibility is somewhat inaccurate,
particularly when it comes to types.  We have TREE_PUBLIC,
DECL_EXTERNAL, DECL_VISIBILITY, DECL_COMDAT, DECL_NOT_REALLY_EXTERN.
It could really do with a through cleanup, but that won't be a simple
task.

The best I could come up with was seeing if the extra scope was a
VAR_DECL, and if that was TREE_PUBLIC and the var was inline (its
COMDATness is sadly not set at that point) or a template
instantiation, then the lambda had linkage.  Otherwise it's as-if it
has no-linkage from the POV of compiler internals.

This is an ABI change (so we should document it), but it's changing
mangling from an unpredictable (in practice) counter, to something the
ABI defines.  So I'm not concerned about mangling-changed warnings, or
preserving the broken mangling under some ABI selection flag.  Code
that did this worked by accident within a single TU.  It'll continue
to work by design there, and across TUs.

	* parser.c (cp_parser_init_declarator): Namespace-scope variables
	provide a lambda scope.
	* tree.c (no_linkage_check): Lambdas with a variable for extra
	scope have a linkage from the variable.

This makes sure that the store a memset is folded to uses a type
covering all bits.

2020-03-18   Richard Biener  <rguenther@suse.de>

	PR middle-end/94206
	* gimple-fold.c (gimple_fold_builtin_memset): Avoid using
	partial int modes or not mode-precision integer types for
	the store.

	* gcc.dg/torture/pr94206.c: New testcase.

Another set of duplicated word fixes for things I've missed last time.
These include e.g. *.cc files I forgot about, or duplicated words at the start
or end of line.

2020-03-18  Jakub Jelinek  <jakub@redhat.com>

	* asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
	in a comment.
	* config/arc/arc.c (frame_stack_add): Likewise.
	* gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
	Likewise.
	* ipa-predicate.c (predicate::remap_after_inlining): Likewise.
	* tree-ssa-strlen.h (handle_printf_call): Likewise.
	* tree-ssa-strlen.c (is_strlen_related_p): Likewise.
	* optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
analyzer/
	* sm-malloc.cc (malloc_state_machine::on_stmt): Fix up duplicated word
	issue in a comment.
	* region-model.cc (region_model::make_region_for_unexpected_tree_code,
	region_model::delete_region_and_descendents): Likewise.
	* engine.cc (class exploded_cluster): Likewise.
	* diagnostic-manager.cc (class path_builder): Likewise.
cp/
	* constraint.cc (resolve_function_concept_check, subsumes_constraints,
	strictly_subsumes): Fix up duplicated word issue in a comment.
	* coroutines.cc (build_init_or_final_await, captures_temporary):
	Likewise.
	* logic.cc (dnf_size_r, cnf_size_r): Likewise.
	* pt.c (append_type_to_template_for_access_check): Likewise.
d/
	* expr.cc (ExprVisitor::visit (CatAssignExp *)): Fix up duplicated
	word issue in a comment.
	* d-target.cc (Target::FPTypeProperties<T>::max): Likewise.
fortran/
	* class.c (generate_finalization_wrapper): Fix up duplicated word
	issue in a comment.
	* trans-types.c (gfc_get_nodesc_array_type): Likewise.

The SYMBOL_TINY_GOT case in aarch64_load_symref_appropriately was
missing support for ILP32.  This caused an ICE on the testcase.

2020-03-18  Duan bo  <duanbo3@huawei.com>

gcc/
	PR target/94201
	* config/aarch64/aarch64.md (ldr_got_tiny): Delete.
	(@ldr_got_tiny_<mode>): New pattern.
	(ldr_got_tiny_sidi): Likewise.
	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
	them to handle SYMBOL_TINY_GOT for ILP32.

gcc/testsuite/
	PR target/94201
	* gcc.target/aarch64/pr94201.c：New test.

Due to a stupid mistake that I can't really explain, I'd got the
treatment of p12-p15 mixed up when adding support for the SVE PCS.
The registers are supposed to be call-preserved rather than
call-clobbered.

The fix is simple, but it has quite a big effect on the PCS tests
(as it should!).

2020-03-18  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
	call-preserved for SVE PCS functions.
	(aarch64_layout_frame): Cope with up to 12 predicate save slots.
	Optimize the case in which there are no following vector save slots.

gcc/testsuite/
	* gcc.target/aarch64/sve/acle/general/cpy_1.c: Leave gaps for in the
	check-function-bodies patterns for p15 to be saved.
	* gcc.target/aarch64/sve/pcs/args_1.c (callee_pred): Expect two
	predicates to be saved.
	* gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c: Expect p12-p15
	to be saved and restored.
	* gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_4_be.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_4_le.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_5_be.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_5_le.c: Likewise.
	* gcc.target/aarch64/sve/pcs/stack_clash_1.c (test_1): Likewise.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_128.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_256.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	(test_4): Expect only 16 bytes of stack to be allocated for the
	predicate save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_512.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	(test_4): Expect only 16 bytes of stack to be allocated for the
	predicate save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	(test_4): Expect only 16 bytes of stack to be allocated for the
	predicate save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	(test_4): Expect only 32 bytes of stack to be allocated for the
	predicate save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_256.c: Use z16 rather
	than p4 to create a vector-sized save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_512.c: Likewise.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c: Likewise.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c: Likewise.

	* testsuite/libgomp.oacc-c++/firstprivate-mappings-1.C: Add
	#define DO_LONG_DOUBLE; set to 1, except for nvidia + gcn.
	* libgomp.oacc-c-c++-common/firstprivate-mappings-1.c: Likewise.

	* g++.dg/goacc/firstprivate-mappings-1.C: Only set DO_LONG_DOUBLE if
	not defined; update comments.
	* c-c++-common/goacc/firstprivate-mappings-1.c: Likewise.

This adds a missing type conversion to build_fold_addr_expr and adjusts
fallout - build_fold_addr_expr was used as a convenience to build an
ADDR_EXPR but some callers do not expect the result to be simplified
to something else.

2020-03-18  Richard Biener  <rguenther@suse.de>

	PR middle-end/94188
	* fold-const.c (build_fold_addr_expr): Convert address to
	correct type.
	* asan.c (maybe_create_ssa_name): Strip useless type conversions.
	* gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
	to build the ADDR_EXPR which we don't really want to simplify.
	* tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
	* tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
	* tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
	(simplify_builtin_call): Strip useless type conversions.
	* tree-ssa-strlen.c (new_strinfo): Likewise.

	* gcc.dg/pr94188.c: New testcase.

The following testcase is accepts-invalid since r7-6608-ga56c0ac0.
Before that change we had this
"deduction guide %qD must be declared in the same scope as %qT"
diagnostics for it, after the change it is expected to be diagnosed
in set_decl_namespace at the not_found: label in there.  On this testcase
nothing is diagnosed though, because set_decl_namespace isn't called at all,
as in_namespace is NULL.

The following patch restores the old warning but does it only in case we
don't call set_decl_namespace.

2020-03-18  Jakub Jelinek  <jakub@redhat.com>

	PR c++/91759
	* decl.c (grokfndecl): Restore old diagnostics about deduction
	guide declared in different scope if in_namespace is NULL_TREE.

	* g++.dg/cpp1z/class-deduction72.C: New test.

-g1 is described in the manual to generate debug info for functions and
external variables. It does that for older debugging formats but not for
DWARF. This change brings DWARF in line with the rest of the debugging
formats and with the manual.

gcc/ChangeLog
2020-03-17  Alexey Neyman  <stilor@att.net>

	PR debug/93751
	* dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
	the debug level is terse and the declaration is public. Do not
	generate type info.
	(dwarf2out_decl): Same.
	(add_type_attribute): Return immediately if debug level is
	terse.

Signed-off-by: Alexey Neyman <stilor@att.net>

The _Tgt and _TgtImpl types that implement type-erasure didn't agree on
the virtual interface, so failed as soon as they were instantiated. With
Clang they failed even sooner. The interface was also dependent on
whether RTTI was enabled or not.

This patch fixes the broken virtual functions and makes the type work
without RTTI, by using a pointer to a specialization of a function
template (similar to the approaches in std::function and std::any).

The changes to the virtual functions would be an ABI change, except that
the previous code didn't even compile if instantiated. This is
experimental TS material anyway.

	PR libstdc++/94203
	* include/experimental/executor (executor::executor(Executor)): Call
	make_shared directly instead of _M_create. Create _Tgt1 object.
	(executor::executor(allocator_arg_t, const ProtoAlloc&, Executor)):
	Call allocate_shared directly instead of _M_create. Create _Tgt2
	object.
	(executor::target_type): Add cast needed for new _Tgt interface.
	(executor::target): Define when RTTI is disabled. Use _Tgt::_M_func.
	(executor::_Tgt): Define the same interface whether RTTI is enabled or
	not.
	(executor::_Tgt::target_type, executor::_Tgt::target): Do not use
	std::type_info in the interface.
	(executor::_Tgt::_M_func): Add data member.
	(executor::_TgtImpl): Replace with _Tgt1 and _Tgt2 class templates.
	(executor::_Tgt1::_S_func): Define function to access target without
	depending on RTTI.
	(executor::_M_create): Remove.
	(operator==, operator!=): Simplify comparisons for executor.
	* include/experimental/socket (is_error_code_enum<socket_errc>):
	Define specialization before use.
	* testsuite/experimental/net/executor/1.cc: New test.

	* g++.dg/debug/dwarf2/const2b.C (dg-do): Fix target selector.

The following testcases ICE, because they contain extern variable
declarations with incomplete enum types that is later completed and after
that those variables are accessed.  The ICEs are because the vars then may have
incorrect DECL_MODE etc., e.g. in the first case the var has SImode
DECL_MODE (the guessed mode for the enum), but the enum then actually has
DImode because its enumerators don't fit into unsigned int.

The following patch fixes it by using C_TYPE_INCOMPLETE_VARS not just on
incomplete struct/union types, but also incomplete enum types.
TYPE_VFIELD can't be used as it is TYPE_MIN_VALUE on ENUMERAL_TYPE,
thankfully TYPE_LANG_SLOT_1 has been used in the C FE only on
FUNCTION_TYPEs.

2020-03-17  Jakub Jelinek  <jakub@redhat.com>

	PR c/94172
	* c-tree.h (C_TYPE_INCOMPLETE_VARS): Define to TYPE_LANG_SLOT_1
	instead of TYPE_VFIELD, and support it on {RECORD,UNION,ENUMERAL}_TYPE.
	(TYPE_ACTUAL_ARG_TYPES): Check that it is only used on FUNCTION_TYPEs.
	* c-decl.c (pushdecl): Push C_TYPE_INCOMPLETE_VARS also to
	ENUMERAL_TYPEs.
	(finish_incomplete_vars): New function, moved from finish_struct.  Use
	relayout_decl instead of layout_decl.
	(finish_struct): Remove obsolete comment about C_TYPE_INCOMPLETE_VARS
	being TYPE_VFIELD.  Use finish_incomplete_vars.
	(finish_enum): Clear C_TYPE_INCOMPLETE_VARS.  Call
	finish_incomplete_vars.
	* c-typeck.c (c_build_qualified_type): Clear C_TYPE_INCOMPLETE_VARS
	also on ENUMERAL_TYPEs.

	* gcc.dg/pr94172-1.c: New test.
	* gcc.dg/pr94172-2.c: New test.

The testcase shows some accepts-invalid (the ones without alignas) and
ice-on-invalid-code (the ones with alignas) cases.
If the enum doesn't have an underlying type and is not a definition,
the caller retries to parse it as elaborated type specifier.
E.g. for enum struct S s it will then pedwarn that elaborated type specifier
shouldn't have the struct/class keywords.
The problem is if the enum specifier is not followed by { when it has
underlying type.  In that case we have already called
cp_parser_parse_definitely to end the tentative parsing started at the
beginning of cp_parser_enum_specifier.  But the
cp_parser_error (parser, "expected %<;%> or %<{%>");
doesn't emit any error because the whole function is called from yet another
tentative parse and the caller starts parsing the elaborated type
specifier where the cp_parser_enum_specifier stopped (i.e. after the
underlying type token(s)).  The ultimate caller than commits the tentative
parsing (and even if it wouldn't, it wouldn't know what kind of error
to report).  I think after seeing enum {,struct,class} : type not being
followed by { or ;, there is no reason not to report it right away, as it
can't be valid C++, which is what the patch does.  Not sure if we shouldn't
also return error_mark_node instead of NULL_TREE, so that the caller doesn't
try to parse it as elaborated type specifier (the patch doesn't do that
right now).

Furthermore, while reading the code, I've noticed that
parser->colon_corrects_to_scope_p is saved and set to false at the start
of the function, but not restored back in some cases.  Don't have a testcase
where this would be a problem, but it just seems wrong.  Either we can in
the two spots replace return NULL_TREE; with { type = NULL_TREE; goto out; }
or we could perhaps abuse warning_sentinel or create a special class with
dtor to clean the flag up.

And lastly, I've fixed some formatting issues in the function while reading
it.

2020-03-17  Jakub Jelinek  <jakub@redhat.com>

	PR c++/90995
	* parser.c (cp_parser_enum_specifier): Use temp_override for
	parser->colon_corrects_to_scope_p, replace goto out with return.
	If scoped enum or enum with underlying type is not followed by
	{ or ;, call cp_parser_commit_to_tentative_parse before calling
	cp_parser_error and make sure to return error_mark_node instead of
	NULL_TREE.  Formatting fixes.

	* g++.dg/cpp0x/enum40.C: New test.

2020-03-17  Richard Sandiford  <richard.sandiford@arm.com>

gcc/testsuite/
	* gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c: Skip for
	-fno-fat-lto-objects.  Use tabs rather than spaces in the
	check-function-bodies code.

gcc.target/aarch64/advsimd-intrinsics/bf16_vldn.c and
gcc.target/aarch64/advsimd-intrinsics/bf16_vstn.c were
failing for big-endian targets because the <Vmtype> in
aarch64_be_ld1<mode> and aarch64_be_st1<mode> had no
expansion for the bfloat16 modes.

2020-03-17  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.

Invocations of the coro-torture.exp like 'coro-torture.exp=some-test.C' were
failing because DEFAULT_CXXFLAGS was undefined.  Fixed by defining this
locally, if it has no pre-existing global value.

This patch supports following MVE ACLE intrinsics with ternary operands.

vabavq_s8, vabavq_s16, vabavq_s32, vbicq_m_n_s16, vbicq_m_n_s32, vbicq_m_n_u16, vbicq_m_n_u32, vcmpeqq_m_f16, vcmpeqq_m_f32, vcvtaq_m_s16_f16, vcvtaq_m_u16_f16, vcvtaq_m_s32_f32, vcvtaq_m_u32_f32, vcvtq_m_f16_s16, vcvtq_m_f16_u16, vcvtq_m_f32_s32, vcvtq_m_f32_u32, vqrshrnbq_n_s16, vqrshrnbq_n_u16, vqrshrnbq_n_s32, vqrshrnbq_n_u32, vqrshrunbq_n_s16, vqrshrunbq_n_s32, vrmlaldavhaq_s32, vrmlaldavhaq_u32, vshlcq_s8, vshlcq_u8, vshlcq_s16, vshlcq_u16, vshlcq_s32, vshlcq_u32, vabavq_s8, vabavq_s16, vabavq_s32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
	Define qualifier for ternary operands.
	(TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vabavq_s8): Define macro.
	(vabavq_s16): Likewise.
	(vabavq_s32): Likewise.
	(vbicq_m_n_s16): Likewise.
	(vbicq_m_n_s32): Likewise.
	(vbicq_m_n_u16): Likewise.
	(vbicq_m_n_u32): Likewise.
	(vcmpeqq_m_f16): Likewise.
	(vcmpeqq_m_f32): Likewise.
	(vcvtaq_m_s16_f16): Likewise.
	(vcvtaq_m_u16_f16): Likewise.
	(vcvtaq_m_s32_f32): Likewise.
	(vcvtaq_m_u32_f32): Likewise.
	(vcvtq_m_f16_s16): Likewise.
	(vcvtq_m_f16_u16): Likewise.
	(vcvtq_m_f32_s32): Likewise.
	(vcvtq_m_f32_u32): Likewise.
	(vqrshrnbq_n_s16): Likewise.
	(vqrshrnbq_n_u16): Likewise.
	(vqrshrnbq_n_s32): Likewise.
	(vqrshrnbq_n_u32): Likewise.
	(vqrshrunbq_n_s16): Likewise.
	(vqrshrunbq_n_s32): Likewise.
	(vrmlaldavhaq_s32): Likewise.
	(vrmlaldavhaq_u32): Likewise.
	(vshlcq_s8): Likewise.
	(vshlcq_u8): Likewise.
	(vshlcq_s16): Likewise.
	(vshlcq_u16): Likewise.
	(vshlcq_s32): Likewise.
	(vshlcq_u32): Likewise.
	(vabavq_u8): Likewise.
	(vabavq_u16): Likewise.
	(vabavq_u32): Likewise.
	(__arm_vabavq_s8): Define intrinsic.
	(__arm_vabavq_s16): Likewise.
	(__arm_vabavq_s32): Likewise.
	(__arm_vabavq_u8): Likewise.
	(__arm_vabavq_u16): Likewise.
	(__arm_vabavq_u32): Likewise.
	(__arm_vbicq_m_n_s16): Likewise.
	(__arm_vbicq_m_n_s32): Likewise.
	(__arm_vbicq_m_n_u16): Likewise.
	(__arm_vbicq_m_n_u32): Likewise.
	(__arm_vqrshrnbq_n_s16): Likewise.
	(__arm_vqrshrnbq_n_u16): Likewise.
	(__arm_vqrshrnbq_n_s32): Likewise.
	(__arm_vqrshrnbq_n_u32): Likewise.
	(__arm_vqrshrunbq_n_s16): Likewise.
	(__arm_vqrshrunbq_n_s32): Likewise.
	(__arm_vrmlaldavhaq_s32): Likewise.
	(__arm_vrmlaldavhaq_u32): Likewise.
	(__arm_vshlcq_s8): Likewise.
	(__arm_vshlcq_u8): Likewise.
	(__arm_vshlcq_s16): Likewise.
	(__arm_vshlcq_u16): Likewise.
	(__arm_vshlcq_s32): Likewise.
	(__arm_vshlcq_u32): Likewise.
	(__arm_vcmpeqq_m_f16): Likewise.
	(__arm_vcmpeqq_m_f32): Likewise.
	(__arm_vcvtaq_m_s16_f16): Likewise.
	(__arm_vcvtaq_m_u16_f16): Likewise.
	(__arm_vcvtaq_m_s32_f32): Likewise.
	(__arm_vcvtaq_m_u32_f32): Likewise.
	(__arm_vcvtq_m_f16_s16): Likewise.
	(__arm_vcvtq_m_f16_u16): Likewise.
	(__arm_vcvtq_m_f32_s32): Likewise.
	(__arm_vcvtq_m_f32_u32): Likewise.
	(vcvtaq_m): Define polymorphic variant.
	(vcvtq_m): Likewise.
	(vabavq): Likewise.
	(vshlcq): Likewise.
	(vbicq_m_n): Likewise.
	(vqrshrnbq_n): Likewise.
	(vqrshrunbq_n): Likewise.
	* config/arm/arm_mve_builtins.def
	(TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
	(TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
	* config/arm/mve.md (VBICQ_M_N): Define iterator.
	(VCVTAQ_M): Likewise.
	(VCVTQ_M_TO_F): Likewise.
	(VQRSHRNBQ_N): Likewise.
	(VABAVQ): Likewise.
	(VSHLCQ): Likewise.
	(VRMLALDAVHAQ): Likewise.
	(mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
	(mve_vcmpeqq_m_f<mode>): Likewise.
	(mve_vcvtaq_m_<supf><mode>): Likewise.
	(mve_vcvtq_m_to_f_<supf><mode>): Likewise.
	(mve_vqrshrnbq_n_<supf><mode>): Likewise.
	(mve_vqrshrunbq_n_s<mode>): Likewise.
	(mve_vrmlaldavhaq_<supf>v4si): Likewise.
	(mve_vabavq_<supf><mode>): Likewise.
	(mve_vshlcq_<supf><mode>): Likewise.
	(mve_vshlcq_<supf><mode>): Likewise.
	(mve_vshlcq_vec_<supf><mode>): Define RTL expand.
	(mve_vshlcq_carry_<supf><mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabavq_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.

This patch supports following MVE ACLE intrinsics with binary operands.

vqmovntq_u16, vqmovnbq_u16, vmulltq_poly_p8, vmullbq_poly_p8, vmovntq_u16, vmovnbq_u16, vmlaldavxq_u16, vmlaldavq_u16, vqmovuntq_s16, vqmovunbq_s16, vshlltq_n_u8, vshllbq_n_u8, vorrq_n_u16, vbicq_n_u16, vcmpneq_n_f16, vcmpneq_f16, vcmpltq_n_f16, vcmpltq_f16, vcmpleq_n_f16, vcmpleq_f16, vcmpgtq_n_f16, vcmpgtq_f16, vcmpgeq_n_f16, vcmpgeq_f16, vcmpeqq_n_f16, vcmpeqq_f16, vsubq_f16, vqmovntq_s16, vqmovnbq_s16, vqdmulltq_s16, vqdmulltq_n_s16, vqdmullbq_s16, vqdmullbq_n_s16, vorrq_f16, vornq_f16, vmulq_n_f16, vmulq_f16, vmovntq_s16, vmovnbq_s16, vmlsldavxq_s16, vmlsldavq_s16, vmlaldavxq_s16, vmlaldavq_s16, vminnmvq_f16, vminnmq_f16, vminnmavq_f16, vminnmaq_f16, vmaxnmvq_f16, vmaxnmq_f16, vmaxnmavq_f16, vmaxnmaq_f16, veorq_f16, vcmulq_rot90_f16, vcmulq_rot270_f16, vcmulq_rot180_f16, vcmulq_f16, vcaddq_rot90_f16, vcaddq_rot270_f16, vbicq_f16, vandq_f16, vaddq_n_f16, vabdq_f16, vshlltq_n_s8, vshllbq_n_s8, vorrq_n_s16, vbicq_n_s16, vqmovntq_u32, vqmovnbq_u32, vmulltq_poly_p16, vmullbq_poly_p16, vmovntq_u32, vmovnbq_u32, vmlaldavxq_u32, vmlaldavq_u32, vqmovuntq_s32, vqmovunbq_s32, vshlltq_n_u16, vshllbq_n_u16, vorrq_n_u32, vbicq_n_u32, vcmpneq_n_f32, vcmpneq_f32, vcmpltq_n_f32, vcmpltq_f32, vcmpleq_n_f32, vcmpleq_f32, vcmpgtq_n_f32, vcmpgtq_f32, vcmpgeq_n_f32, vcmpgeq_f32, vcmpeqq_n_f32, vcmpeqq_f32, vsubq_f32, vqmovntq_s32, vqmovnbq_s32, vqdmulltq_s32, vqdmulltq_n_s32, vqdmullbq_s32, vqdmullbq_n_s32, vorrq_f32, vornq_f32, vmulq_n_f32, vmulq_f32, vmovntq_s32, vmovnbq_s32, vmlsldavxq_s32, vmlsldavq_s32, vmlaldavxq_s32, vmlaldavq_s32, vminnmvq_f32, vminnmq_f32, vminnmavq_f32, vminnmaq_f32, vmaxnmvq_f32, vmaxnmq_f32, vmaxnmavq_f32, vmaxnmaq_f32, veorq_f32, vcmulq_rot90_f32, vcmulq_rot270_f32, vcmulq_rot180_f32, vcmulq_f32, vcaddq_rot90_f32, vcaddq_rot270_f32, vbicq_f32, vandq_f32, vaddq_n_f32, vabdq_f32, vshlltq_n_s16, vshllbq_n_s16, vorrq_n_s32, vbicq_n_s32, vrmlaldavhq_u32, vctp8q_m, vctp64q_m, vctp32q_m, vctp16q_m, vaddlvaq_u32, vrmlsldavhxq_s32, vrmlsldavhq_s32, vrmlaldavhxq_s32, vrmlaldavhq_s32, vcvttq_f16_f32, vcvtbq_f16_f32, vaddlvaq_s32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

The above intrinsics are defined using the already defined builtin qualifiers BINOP_NONE_NONE_IMM, BINOP_NONE_NONE_NONE, BINOP_UNONE_NONE_NONE, BINOP_UNONE_UNONE_IMM, BINOP_UNONE_UNONE_NONE, BINOP_UNONE_UNONE_UNONE.

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vqmovntq_u16): Define macro.
	(vqmovnbq_u16): Likewise.
	(vmulltq_poly_p8): Likewise.
	(vmullbq_poly_p8): Likewise.
	(vmovntq_u16): Likewise.
	(vmovnbq_u16): Likewise.
	(vmlaldavxq_u16): Likewise.
	(vmlaldavq_u16): Likewise.
	(vqmovuntq_s16): Likewise.
	(vqmovunbq_s16): Likewise.
	(vshlltq_n_u8): Likewise.
	(vshllbq_n_u8): Likewise.
	(vorrq_n_u16): Likewise.
	(vbicq_n_u16): Likewise.
	(vcmpneq_n_f16): Likewise.
	(vcmpneq_f16): Likewise.
	(vcmpltq_n_f16): Likewise.
	(vcmpltq_f16): Likewise.
	(vcmpleq_n_f16): Likewise.
	(vcmpleq_f16): Likewise.
	(vcmpgtq_n_f16): Likewise.
	(vcmpgtq_f16): Likewise.
	(vcmpgeq_n_f16): Likewise.
	(vcmpgeq_f16): Likewise.
	(vcmpeqq_n_f16): Likewise.
	(vcmpeqq_f16): Likewise.
	(vsubq_f16): Likewise.
	(vqmovntq_s16): Likewise.
	(vqmovnbq_s16): Likewise.
	(vqdmulltq_s16): Likewise.
	(vqdmulltq_n_s16): Likewise.
	(vqdmullbq_s16): Likewise.
	(vqdmullbq_n_s16): Likewise.
	(vorrq_f16): Likewise.
	(vornq_f16): Likewise.
	(vmulq_n_f16): Likewise.
	(vmulq_f16): Likewise.
	(vmovntq_s16): Likewise.
	(vmovnbq_s16): Likewise.
	(vmlsldavxq_s16): Likewise.
	(vmlsldavq_s16): Likewise.
	(vmlaldavxq_s16): Likewise.
	(vmlaldavq_s16): Likewise.
	(vminnmvq_f16): Likewise.
	(vminnmq_f16): Likewise.
	(vminnmavq_f16): Likewise.
	(vminnmaq_f16): Likewise.
	(vmaxnmvq_f16): Likewise.
	(vmaxnmq_f16): Likewise.
	(vmaxnmavq_f16): Likewise.
	(vmaxnmaq_f16): Likewise.
	(veorq_f16): Likewise.
	(vcmulq_rot90_f16): Likewise.
	(vcmulq_rot270_f16): Likewise.
	(vcmulq_rot180_f16): Likewise.
	(vcmulq_f16): Likewise.
	(vcaddq_rot90_f16): Likewise.
	(vcaddq_rot270_f16): Likewise.
	(vbicq_f16): Likewise.
	(vandq_f16): Likewise.
	(vaddq_n_f16): Likewise.
	(vabdq_f16): Likewise.
	(vshlltq_n_s8): Likewise.
	(vshllbq_n_s8): Likewise.
	(vorrq_n_s16): Likewise.
	(vbicq_n_s16): Likewise.
	(vqmovntq_u32): Likewise.
	(vqmovnbq_u32): Likewise.
	(vmulltq_poly_p16): Likewise.
	(vmullbq_poly_p16): Likewise.
	(vmovntq_u32): Likewise.
	(vmovnbq_u32): Likewise.
	(vmlaldavxq_u32): Likewise.
	(vmlaldavq_u32): Likewise.
	(vqmovuntq_s32): Likewise.
	(vqmovunbq_s32): Likewise.
	(vshlltq_n_u16): Likewise.
	(vshllbq_n_u16): Likewise.
	(vorrq_n_u32): Likewise.
	(vbicq_n_u32): Likewise.
	(vcmpneq_n_f32): Likewise.
	(vcmpneq_f32): Likewise.
	(vcmpltq_n_f32): Likewise.
	(vcmpltq_f32): Likewise.
	(vcmpleq_n_f32): Likewise.
	(vcmpleq_f32): Likewise.
	(vcmpgtq_n_f32): Likewise.
	(vcmpgtq_f32): Likewise.
	(vcmpgeq_n_f32): Likewise.
	(vcmpgeq_f32): Likewise.
	(vcmpeqq_n_f32): Likewise.
	(vcmpeqq_f32): Likewise.
	(vsubq_f32): Likewise.
	(vqmovntq_s32): Likewise.
	(vqmovnbq_s32): Likewise.
	(vqdmulltq_s32): Likewise.
	(vqdmulltq_n_s32): Likewise.
	(vqdmullbq_s32): Likewise.
	(vqdmullbq_n_s32): Likewise.
	(vorrq_f32): Likewise.
	(vornq_f32): Likewise.
	(vmulq_n_f32): Likewise.
	(vmulq_f32): Likewise.
	(vmovntq_s32): Likewise.
	(vmovnbq_s32): Likewise.
	(vmlsldavxq_s32): Likewise.
	(vmlsldavq_s32): Likewise.
	(vmlaldavxq_s32): Likewise.
	(vmlaldavq_s32): Likewise.
	(vminnmvq_f32): Likewise.
	(vminnmq_f32): Likewise.
	(vminnmavq_f32): Likewise.
	(vminnmaq_f32): Likewise.
	(vmaxnmvq_f32): Likewise.
	(vmaxnmq_f32): Likewise.
	(vmaxnmavq_f32): Likewise.
	(vmaxnmaq_f32): Likewise.
	(veorq_f32): Likewise.
	(vcmulq_rot90_f32): Likewise.
	(vcmulq_rot270_f32): Likewise.
	(vcmulq_rot180_f32): Likewise.
	(vcmulq_f32): Likewise.
	(vcaddq_rot90_f32): Likewise.
	(vcaddq_rot270_f32): Likewise.
	(vbicq_f32): Likewise.
	(vandq_f32): Likewise.
	(vaddq_n_f32): Likewise.
	(vabdq_f32): Likewise.
	(vshlltq_n_s16): Likewise.
	(vshllbq_n_s16): Likewise.
	(vorrq_n_s32): Likewise.
	(vbicq_n_s32): Likewise.
	(vrmlaldavhq_u32): Likewise.
	(vctp8q_m): Likewise.
	(vctp64q_m): Likewise.
	(vctp32q_m): Likewise.
	(vctp16q_m): Likewise.
	(vaddlvaq_u32): Likewise.
	(vrmlsldavhxq_s32): Likewise.
	(vrmlsldavhq_s32): Likewise.
	(vrmlaldavhxq_s32): Likewise.
	(vrmlaldavhq_s32): Likewise.
	(vcvttq_f16_f32): Likewise.
	(vcvtbq_f16_f32): Likewise.
	(vaddlvaq_s32): Likewise.
	(__arm_vqmovntq_u16): Define intrinsic.
	(__arm_vqmovnbq_u16): Likewise.
	(__arm_vmulltq_poly_p8): Likewise.
	(__arm_vmullbq_poly_p8): Likewise.
	(__arm_vmovntq_u16): Likewise.
	(__arm_vmovnbq_u16): Likewise.
	(__arm_vmlaldavxq_u16): Likewise.
	(__arm_vmlaldavq_u16): Likewise.
	(__arm_vqmovuntq_s16): Likewise.
	(__arm_vqmovunbq_s16): Likewise.
	(__arm_vshlltq_n_u8): Likewise.
	(__arm_vshllbq_n_u8): Likewise.
	(__arm_vorrq_n_u16): Likewise.
	(__arm_vbicq_n_u16): Likewise.
	(__arm_vcmpneq_n_f16): Likewise.
	(__arm_vcmpneq_f16): Likewise.
	(__arm_vcmpltq_n_f16): Likewise.
	(__arm_vcmpltq_f16): Likewise.
	(__arm_vcmpleq_n_f16): Likewise.
	(__arm_vcmpleq_f16): Likewise.
	(__arm_vcmpgtq_n_f16): Likewise.
	(__arm_vcmpgtq_f16): Likewise.
	(__arm_vcmpgeq_n_f16): Likewise.
	(__arm_vcmpgeq_f16): Likewise.
	(__arm_vcmpeqq_n_f16): Likewise.
	(__arm_vcmpeqq_f16): Likewise.
	(__arm_vsubq_f16): Likewise.
	(__arm_vqmovntq_s16): Likewise.
	(__arm_vqmovnbq_s16): Likewise.
	(__arm_vqdmulltq_s16): Likewise.
	(__arm_vqdmulltq_n_s16): Likewise.
	(__arm_vqdmullbq_s16): Likewise.
	(__arm_vqdmullbq_n_s16): Likewise.
	(__arm_vorrq_f16): Likewise.
	(__arm_vornq_f16): Likewise.
	(__arm_vmulq_n_f16): Likewise.
	(__arm_vmulq_f16): Likewise.
	(__arm_vmovntq_s16): Likewise.
	(__arm_vmovnbq_s16): Likewise.
	(__arm_vmlsldavxq_s16): Likewise.
	(__arm_vmlsldavq_s16): Likewise.
	(__arm_vmlaldavxq_s16): Likewise.
	(__arm_vmlaldavq_s16): Likewise.
	(__arm_vminnmvq_f16): Likewise.
	(__arm_vminnmq_f16): Likewise.
	(__arm_vminnmavq_f16): Likewise.
	(__arm_vminnmaq_f16): Likewise.
	(__arm_vmaxnmvq_f16): Likewise.
	(__arm_vmaxnmq_f16): Likewise.
	(__arm_vmaxnmavq_f16): Likewise.
	(__arm_vmaxnmaq_f16): Likewise.
	(__arm_veorq_f16): Likewise.
	(__arm_vcmulq_rot90_f16): Likewise.
	(__arm_vcmulq_rot270_f16): Likewise.
	(__arm_vcmulq_rot180_f16): Likewise.
	(__arm_vcmulq_f16): Likewise.
	(__arm_vcaddq_rot90_f16): Likewise.
	(__arm_vcaddq_rot270_f16): Likewise.
	(__arm_vbicq_f16): Likewise.
	(__arm_vandq_f16): Likewise.
	(__arm_vaddq_n_f16): Likewise.
	(__arm_vabdq_f16): Likewise.
	(__arm_vshlltq_n_s8): Likewise.
	(__arm_vshllbq_n_s8): Likewise.
	(__arm_vorrq_n_s16): Likewise.
	(__arm_vbicq_n_s16): Likewise.
	(__arm_vqmovntq_u32): Likewise.
	(__arm_vqmovnbq_u32): Likewise.
	(__arm_vmulltq_poly_p16): Likewise.
	(__arm_vmullbq_poly_p16): Likewise.
	(__arm_vmovntq_u32): Likewise.
	(__arm_vmovnbq_u32): Likewise.
	(__arm_vmlaldavxq_u32): Likewise.
	(__arm_vmlaldavq_u32): Likewise.
	(__arm_vqmovuntq_s32): Likewise.
	(__arm_vqmovunbq_s32): Likewise.
	(__arm_vshlltq_n_u16): Likewise.
	(__arm_vshllbq_n_u16): Likewise.
	(__arm_vorrq_n_u32): Likewise.
	(__arm_vbicq_n_u32): Likewise.
	(__arm_vcmpneq_n_f32): Likewise.
	(__arm_vcmpneq_f32): Likewise.
	(__arm_vcmpltq_n_f32): Likewise.
	(__arm_vcmpltq_f32): Likewise.
	(__arm_vcmpleq_n_f32): Likewise.
	(__arm_vcmpleq_f32): Likewise.
	(__arm_vcmpgtq_n_f32): Likewise.
	(__arm_vcmpgtq_f32): Likewise.
	(__arm_vcmpgeq_n_f32): Likewise.
	(__arm_vcmpgeq_f32): Likewise.
	(__arm_vcmpeqq_n_f32): Likewise.
	(__arm_vcmpeqq_f32): Likewise.
	(__arm_vsubq_f32): Likewise.
	(__arm_vqmovntq_s32): Likewise.
	(__arm_vqmovnbq_s32): Likewise.
	(__arm_vqdmulltq_s32): Likewise.
	(__arm_vqdmulltq_n_s32): Likewise.
	(__arm_vqdmullbq_s32): Likewise.
	(__arm_vqdmullbq_n_s32): Likewise.
	(__arm_vorrq_f32): Likewise.
	(__arm_vornq_f32): Likewise.
	(__arm_vmulq_n_f32): Likewise.
	(__arm_vmulq_f32): Likewise.
	(__arm_vmovntq_s32): Likewise.
	(__arm_vmovnbq_s32): Likewise.
	(__arm_vmlsldavxq_s32): Likewise.
	(__arm_vmlsldavq_s32): Likewise.
	(__arm_vmlaldavxq_s32): Likewise.
	(__arm_vmlaldavq_s32): Likewise.
	(__arm_vminnmvq_f32): Likewise.
	(__arm_vminnmq_f32): Likewise.
	(__arm_vminnmavq_f32): Likewise.
	(__arm_vminnmaq_f32): Likewise.
	(__arm_vmaxnmvq_f32): Likewise.
	(__arm_vmaxnmq_f32): Likewise.
	(__arm_vmaxnmavq_f32): Likewise.
	(__arm_vmaxnmaq_f32): Likewise.
	(__arm_veorq_f32): Likewise.
	(__arm_vcmulq_rot90_f32): Likewise.
	(__arm_vcmulq_rot270_f32): Likewise.
	(__arm_vcmulq_rot180_f32): Likewise.
	(__arm_vcmulq_f32): Likewise.
	(__arm_vcaddq_rot90_f32): Likewise.
	(__arm_vcaddq_rot270_f32): Likewise.
	(__arm_vbicq_f32): Likewise.
	(__arm_vandq_f32): Likewise.
	(__arm_vaddq_n_f32): Likewise.
	(__arm_vabdq_f32): Likewise.
	(__arm_vshlltq_n_s16): Likewise.
	(__arm_vshllbq_n_s16): Likewise.
	(__arm_vorrq_n_s32): Likewise.
	(__arm_vbicq_n_s32): Likewise.
	(__arm_vrmlaldavhq_u32): Likewise.
	(__arm_vctp8q_m): Likewise.
	(__arm_vctp64q_m): Likewise.
	(__arm_vctp32q_m): Likewise.
	(__arm_vctp16q_m): Likewise.
	(__arm_vaddlvaq_u32): Likewise.
	(__arm_vrmlsldavhxq_s32): Likewise.
	(__arm_vrmlsldavhq_s32): Likewise.
	(__arm_vrmlaldavhxq_s32): Likewise.
	(__arm_vrmlaldavhq_s32): Likewise.
	(__arm_vcvttq_f16_f32): Likewise.
	(__arm_vcvtbq_f16_f32): Likewise.
	(__arm_vaddlvaq_s32): Likewise.
	(vst4q): Define polymorphic variant.
	(vrndxq): Likewise.
	(vrndq): Likewise.
	(vrndpq): Likewise.
	(vrndnq): Likewise.
	(vrndmq): Likewise.
	(vrndaq): Likewise.
	(vrev64q): Likewise.
	(vnegq): Likewise.
	(vdupq_n): Likewise.
	(vabsq): Likewise.
	(vrev32q): Likewise.
	(vcvtbq_f32): Likewise.
	(vcvttq_f32): Likewise.
	(vcvtq): Likewise.
	(vsubq_n): Likewise.
	(vbrsrq_n): Likewise.
	(vcvtq_n): Likewise.
	(vsubq): Likewise.
	(vorrq): Likewise.
	(vabdq): Likewise.
	(vaddq_n): Likewise.
	(vandq): Likewise.
	(vbicq): Likewise.
	(vornq): Likewise.
	(vmulq_n): Likewise.
	(vmulq): Likewise.
	(vcaddq_rot270): Likewise.
	(vcmpeqq_n): Likewise.
	(vcmpeqq): Likewise.
	(vcaddq_rot90): Likewise.
	(vcmpgeq_n): Likewise.
	(vcmpgeq): Likewise.
	(vcmpgtq_n): Likewise.
	(vcmpgtq): Likewise.
	(vcmpgtq): Likewise.
	(vcmpleq_n): Likewise.
	(vcmpleq_n): Likewise.
	(vcmpleq): Likewise.
	(vcmpleq): Likewise.
	(vcmpltq_n): Likewise.
	(vcmpltq_n): Likewise.
	(vcmpltq): Likewise.
	(vcmpltq): Likewise.
	(vcmpneq_n): Likewise.
	(vcmpneq_n): Likewise.
	(vcmpneq): Likewise.
	(vcmpneq): Likewise.
	(vcmulq): Likewise.
	(vcmulq): Likewise.
	(vcmulq_rot180): Likewise.
	(vcmulq_rot180): Likewise.
	(vcmulq_rot270): Likewise.
	(vcmulq_rot270): Likewise.
	(vcmulq_rot90): Likewise.
	(vcmulq_rot90): Likewise.
	(veorq): Likewise.
	(veorq): Likewise.
	(vmaxnmaq): Likewise.
	(vmaxnmaq): Likewise.
	(vmaxnmavq): Likewise.
	(vmaxnmavq): Likewise.
	(vmaxnmq): Likewise.
	(vmaxnmq): Likewise.
	(vmaxnmvq): Likewise.
	(vmaxnmvq): Likewise.
	(vminnmaq): Likewise.
	(vminnmaq): Likewise.
	(vminnmavq): Likewise.
	(vminnmavq): Likewise.
	(vminnmq): Likewise.
	(vminnmq): Likewise.
	(vminnmvq): Likewise.
	(vminnmvq): Likewise.
	(vbicq_n): Likewise.
	(vqmovntq): Likewise.
	(vqmovntq): Likewise.
	(vqmovnbq): Likewise.
	(vqmovnbq): Likewise.
	(vmulltq_poly): Likewise.
	(vmulltq_poly): Likewise.
	(vmullbq_poly): Likewise.
	(vmullbq_poly): Likewise.
	(vmovntq): Likewise.
	(vmovntq): Likewise.
	(vmovnbq): Likewise.
	(vmovnbq): Likewise.
	(vmlaldavxq): Likewise.
	(vmlaldavxq): Likewise.
	(vqmovuntq): Likewise.
	(vqmovuntq): Likewise.
	(vshlltq_n): Likewise.
	(vshlltq_n): Likewise.
	(vshllbq_n): Likewise.
	(vshllbq_n): Likewise.
	(vorrq_n): Likewise.
	(vorrq_n): Likewise.
	(vmlaldavq): Likewise.
	(vmlaldavq): Likewise.
	(vqmovunbq): Likewise.
	(vqmovunbq): Likewise.
	(vqdmulltq_n): Likewise.
	(vqdmulltq_n): Likewise.
	(vqdmulltq): Likewise.
	(vqdmulltq): Likewise.
	(vqdmullbq_n): Likewise.
	(vqdmullbq_n): Likewise.
	(vqdmullbq): Likewise.
	(vqdmullbq): Likewise.
	(vaddlvaq): Likewise.
	(vaddlvaq): Likewise.
	(vrmlaldavhq): Likewise.
	(vrmlaldavhq): Likewise.
	(vrmlaldavhxq): Likewise.
	(vrmlaldavhxq): Likewise.
	(vrmlsldavhq): Likewise.
	(vrmlsldavhq): Likewise.
	(vrmlsldavhxq): Likewise.
	(vrmlsldavhxq): Likewise.
	(vmlsldavxq): Likewise.
	(vmlsldavxq): Likewise.
	(vmlsldavq): Likewise.
	(vmlsldavq): Likewise.
	* config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
	(BINOP_NONE_NONE_NONE): Likewise.
	(BINOP_UNONE_NONE_NONE): Likewise.
	(BINOP_UNONE_UNONE_IMM): Likewise.
	(BINOP_UNONE_UNONE_NONE): Likewise.
	(BINOP_UNONE_UNONE_UNONE): Likewise.
	* config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
	(mve_vaddlvaq_<supf>v4si): Likewise.
	(mve_vaddq_n_f<mode>): Likewise.
	(mve_vandq_f<mode>): Likewise.
	(mve_vbicq_f<mode>): Likewise.
	(mve_vbicq_n_<supf><mode>): Likewise.
	(mve_vcaddq_rot270_f<mode>): Likewise.
	(mve_vcaddq_rot90_f<mode>): Likewise.
	(mve_vcmpeqq_f<mode>): Likewise.
	(mve_vcmpeqq_n_f<mode>): Likewise.
	(mve_vcmpgeq_f<mode>): Likewise.
	(mve_vcmpgeq_n_f<mode>): Likewise.
	(mve_vcmpgtq_f<mode>): Likewise.
	(mve_vcmpgtq_n_f<mode>): Likewise.
	(mve_vcmpleq_f<mode>): Likewise.
	(mve_vcmpleq_n_f<mode>): Likewise.
	(mve_vcmpltq_f<mode>): Likewise.
	(mve_vcmpltq_n_f<mode>): Likewise.
	(mve_vcmpneq_f<mode>): Likewise.
	(mve_vcmpneq_n_f<mode>): Likewise.
	(mve_vcmulq_f<mode>): Likewise.
	(mve_vcmulq_rot180_f<mode>): Likewise.
	(mve_vcmulq_rot270_f<mode>): Likewise.
	(mve_vcmulq_rot90_f<mode>): Likewise.
	(mve_vctp<mode1>q_mhi): Likewise.
	(mve_vcvtbq_f16_f32v8hf): Likewise.
	(mve_vcvttq_f16_f32v8hf): Likewise.
	(mve_veorq_f<mode>): Likewise.
	(mve_vmaxnmaq_f<mode>): Likewise.
	(mve_vmaxnmavq_f<mode>): Likewise.
	(mve_vmaxnmq_f<mode>): Likewise.
	(mve_vmaxnmvq_f<mode>): Likewise.
	(mve_vminnmaq_f<mode>): Likewise.
	(mve_vminnmavq_f<mode>): Likewise.
	(mve_vminnmq_f<mode>): Likewise.
	(mve_vminnmvq_f<mode>): Likewise.
	(mve_vmlaldavq_<supf><mode>): Likewise.
	(mve_vmlaldavxq_<supf><mode>): Likewise.
	(mve_vmlsldavq_s<mode>): Likewise.
	(mve_vmlsldavxq_s<mode>): Likewise.
	(mve_vmovnbq_<supf><mode>): Likewise.
	(mve_vmovntq_<supf><mode>): Likewise.
	(mve_vmulq_f<mode>): Likewise.
	(mve_vmulq_n_f<mode>): Likewise.
	(mve_vornq_f<mode>): Likewise.
	(mve_vorrq_f<mode>): Likewise.
	(mve_vorrq_n_<supf><mode>): Likewise.
	(mve_vqdmullbq_n_s<mode>): Likewise.
	(mve_vqdmullbq_s<mode>): Likewise.
	(mve_vqdmulltq_n_s<mode>): Likewise.
	(mve_vqdmulltq_s<mode>): Likewise.
	(mve_vqmovnbq_<supf><mode>): Likewise.
	(mve_vqmovntq_<supf><mode>): Likewise.
	(mve_vqmovunbq_s<mode>): Likewise.
	(mve_vqmovuntq_s<mode>): Likewise.
	(mve_vrmlaldavhxq_sv4si): Likewise.
	(mve_vrmlsldavhq_sv4si): Likewise.
	(mve_vrmlsldavhxq_sv4si): Likewise.
	(mve_vshllbq_n_<supf><mode>): Likewise.
	(mve_vshlltq_n_<supf><mode>): Likewise.
	(mve_vsubq_f<mode>): Likewise.
	(mve_vmulltq_poly_p<mode>): Likewise.
	(mve_vmullbq_poly_p<mode>): Likewise.
	(mve_vrmlaldavhq_<supf>v4si): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabdq_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavxq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.

This patch supports following MVE ACLE intrinsics with binary operands.

vsubq_u8, vsubq_n_u8, vrmulhq_u8, vrhaddq_u8, vqsubq_u8, vqsubq_n_u8, vqaddq_u8,
vqaddq_n_u8, vorrq_u8, vornq_u8, vmulq_u8, vmulq_n_u8, vmulltq_int_u8, vmullbq_int_u8,
vmulhq_u8, vmladavq_u8, vminvq_u8, vminq_u8, vmaxvq_u8, vmaxq_u8, vhsubq_u8, vhsubq_n_u8,
vhaddq_u8, vhaddq_n_u8, veorq_u8, vcmpneq_n_u8, vcmphiq_u8, vcmphiq_n_u8, vcmpeqq_u8,
vcmpeqq_n_u8, vcmpcsq_u8, vcmpcsq_n_u8, vcaddq_rot90_u8, vcaddq_rot270_u8, vbicq_u8,
vandq_u8, vaddvq_p_u8, vaddvaq_u8, vaddq_n_u8, vabdq_u8, vshlq_r_u8, vrshlq_u8,
vrshlq_n_u8, vqshlq_u8, vqshlq_r_u8, vqrshlq_u8, vqrshlq_n_u8, vminavq_s8, vminaq_s8,
vmaxavq_s8, vmaxaq_s8, vbrsrq_n_u8, vshlq_n_u8, vrshrq_n_u8, vqshlq_n_u8, vcmpneq_n_s8,
vcmpltq_s8, vcmpltq_n_s8, vcmpleq_s8, vcmpleq_n_s8, vcmpgtq_s8, vcmpgtq_n_s8, vcmpgeq_s8,
vcmpgeq_n_s8, vcmpeqq_s8, vcmpeqq_n_s8, vqshluq_n_s8, vaddvq_p_s8, vsubq_s8, vsubq_n_s8,
vshlq_r_s8, vrshlq_s8, vrshlq_n_s8, vrmulhq_s8, vrhaddq_s8, vqsubq_s8, vqsubq_n_s8,
vqshlq_s8, vqshlq_r_s8, vqrshlq_s8, vqrshlq_n_s8, vqrdmulhq_s8, vqrdmulhq_n_s8, vqdmulhq_s8,
vqdmulhq_n_s8, vqaddq_s8, vqaddq_n_s8, vorrq_s8, vornq_s8, vmulq_s8, vmulq_n_s8, vmulltq_int_s8,
vmullbq_int_s8, vmulhq_s8, vmlsdavxq_s8, vmlsdavq_s8, vmladavxq_s8, vmladavq_s8, vminvq_s8,
vminq_s8, vmaxvq_s8, vmaxq_s8, vhsubq_s8, vhsubq_n_s8, vhcaddq_rot90_s8, vhcaddq_rot270_s8,
vhaddq_s8, vhaddq_n_s8, veorq_s8, vcaddq_rot90_s8, vcaddq_rot270_s8, vbrsrq_n_s8, vbicq_s8,
vandq_s8, vaddvaq_s8, vaddq_n_s8, vabdq_s8, vshlq_n_s8, vrshrq_n_s8, vqshlq_n_s8, vsubq_u16,
vsubq_n_u16, vrmulhq_u16, vrhaddq_u16, vqsubq_u16, vqsubq_n_u16, vqaddq_u16, vqaddq_n_u16,
vorrq_u16, vornq_u16, vmulq_u16, vmulq_n_u16, vmulltq_int_u16, vmullbq_int_u16, vmulhq_u16,
vmladavq_u16, vminvq_u16, vminq_u16, vmaxvq_u16, vmaxq_u16, vhsubq_u16, vhsubq_n_u16,
vhaddq_u16, vhaddq_n_u16, veorq_u16, vcmpneq_n_u16, vcmphiq_u16, vcmphiq_n_u16, vcmpeqq_u16,
vcmpeqq_n_u16, vcmpcsq_u16, vcmpcsq_n_u16, vcaddq_rot90_u16, vcaddq_rot270_u16, vbicq_u16,
vandq_u16, vaddvq_p_u16, vaddvaq_u16, vaddq_n_u16, vabdq_u16, vshlq_r_u16, vrshlq_u16,
vrshlq_n_u16, vqshlq_u16, vqshlq_r_u16, vqrshlq_u16, vqrshlq_n_u16, vminavq_s16, vminaq_s16,
vmaxavq_s16, vmaxaq_s16, vbrsrq_n_u16, vshlq_n_u16, vrshrq_n_u16, vqshlq_n_u16, vcmpneq_n_s16,
vcmpltq_s16, vcmpltq_n_s16, vcmpleq_s16, vcmpleq_n_s16, vcmpgtq_s16, vcmpgtq_n_s16,
vcmpgeq_s16, vcmpgeq_n_s16, vcmpeqq_s16, vcmpeqq_n_s16, vqshluq_n_s16, vaddvq_p_s16, vsubq_s16,
vsubq_n_s16, vshlq_r_s16, vrshlq_s16, vrshlq_n_s16, vrmulhq_s16, vrhaddq_s16, vqsubq_s16,
vqsubq_n_s16, vqshlq_s16, vqshlq_r_s16, vqrshlq_s16, vqrshlq_n_s16, vqrdmulhq_s16,
vqrdmulhq_n_s16, vqdmulhq_s16, vqdmulhq_n_s16, vqaddq_s16, vqaddq_n_s16, vorrq_s16, vornq_s16,
vmulq_s16, vmulq_n_s16, vmulltq_int_s16, vmullbq_int_s16, vmulhq_s16, vmlsdavxq_s16, vmlsdavq_s16,
vmladavxq_s16, vmladavq_s16, vminvq_s16, vminq_s16, vmaxvq_s16, vmaxq_s16, vhsubq_s16,
vhsubq_n_s16, vhcaddq_rot90_s16, vhcaddq_rot270_s16, vhaddq_s16, vhaddq_n_s16, veorq_s16,
vcaddq_rot90_s16, vcaddq_rot270_s16, vbrsrq_n_s16, vbicq_s16, vandq_s16, vaddvaq_s16, vaddq_n_s16,
vabdq_s16, vshlq_n_s16, vrshrq_n_s16, vqshlq_n_s16, vsubq_u32, vsubq_n_u32, vrmulhq_u32,
vrhaddq_u32, vqsubq_u32, vqsubq_n_u32, vqaddq_u32, vqaddq_n_u32, vorrq_u32, vornq_u32, vmulq_u32,
vmulq_n_u32, vmulltq_int_u32, vmullbq_int_u32, vmulhq_u32, vmladavq_u32, vminvq_u32, vminq_u32,
vmaxvq_u32, vmaxq_u32, vhsubq_u32, vhsubq_n_u32, vhaddq_u32, vhaddq_n_u32, veorq_u32, vcmpneq_n_u32,
vcmphiq_u32, vcmphiq_n_u32, vcmpeqq_u32, vcmpeqq_n_u32, vcmpcsq_u32, vcmpcsq_n_u32,
vcaddq_rot90_u32, vcaddq_rot270_u32, vbicq_u32, vandq_u32, vaddvq_p_u32, vaddvaq_u32, vaddq_n_u32,
vabdq_u32, vshlq_r_u32, vrshlq_u32, vrshlq_n_u32, vqshlq_u32, vqshlq_r_u32, vqrshlq_u32, vqrshlq_n_u32,
vminavq_s32, vminaq_s32, vmaxavq_s32, vmaxaq_s32, vbrsrq_n_u32, vshlq_n_u32, vrshrq_n_u32,
vqshlq_n_u32, vcmpneq_n_s32, vcmpltq_s32, vcmpltq_n_s32, vcmpleq_s32, vcmpleq_n_s32, vcmpgtq_s32,
vcmpgtq_n_s32, vcmpgeq_s32, vcmpgeq_n_s32, vcmpeqq_s32, vcmpeqq_n_s32, vqshluq_n_s32, vaddvq_p_s32,
vsubq_s32, vsubq_n_s32, vshlq_r_s32, vrshlq_s32, vrshlq_n_s32, vrmulhq_s32, vrhaddq_s32, vqsubq_s32,
vqsubq_n_s32, vqshlq_s32, vqshlq_r_s32, vqrshlq_s32, vqrshlq_n_s32, vqrdmulhq_s32, vqrdmulhq_n_s32,
vqdmulhq_s32, vqdmulhq_n_s32, vqaddq_s32, vqaddq_n_s32, vorrq_s32, vornq_s32, vmulq_s32, vmulq_n_s32,
vmulltq_int_s32, vmullbq_int_s32, vmulhq_s32, vmlsdavxq_s32, vmlsdavq_s32, vmladavxq_s32, vmladavq_s32,
vminvq_s32, vminq_s32, vmaxvq_s32, vmaxq_s32, vhsubq_s32, vhsubq_n_s32, vhcaddq_rot90_s32,
vhcaddq_rot270_s32, vhaddq_s32, vhaddq_n_s32, veorq_s32, vcaddq_rot90_s32, vcaddq_rot270_s32,
vbrsrq_n_s32, vbicq_s32, vandq_s32, vaddvaq_s32, vaddq_n_s32, vabdq_s32, vshlq_n_s32, vrshrq_n_s32,
vqshlq_n_s32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

In this patch new constraints "Ra" and "Rg" are added.
Ra checks the constant is with in the range of 0 to 7 where as Rg checks that the constant is one among
1, 2, 4 and 8.

Also a new predicates "mve_imm_7" and "mve_imm_selective_upto_8" are added, to check the the matching
constraint Ra and Rg respectively.

The above intrinsics are defined using the already defined builtin qualifiers BINOP_NONE_NONE_IMM, BINOP_NONE_NONE_NONE,
BINOP_NONE_NONE_UNONE, BINOP_UNONE_NONE_IMM, BINOP_UNONE_NONE_NONE, BINOP_UNONE_UNONE_IMM, BINOP_UNONE_UNONE_NONE,
BINOP_UNONE_UNONE_UNONE.

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vsubq_u8): Define macro.
	(vsubq_n_u8): Likewise.
	(vrmulhq_u8): Likewise.
	(vrhaddq_u8): Likewise.
	(vqsubq_u8): Likewise.
	(vqsubq_n_u8): Likewise.
	(vqaddq_u8): Likewise.
	(vqaddq_n_u8): Likewise.
	(vorrq_u8): Likewise.
	(vornq_u8): Likewise.
	(vmulq_u8): Likewise.
	(vmulq_n_u8): Likewise.
	(vmulltq_int_u8): Likewise.
	(vmullbq_int_u8): Likewise.
	(vmulhq_u8): Likewise.
	(vmladavq_u8): Likewise.
	(vminvq_u8): Likewise.
	(vminq_u8): Likewise.
	(vmaxvq_u8): Likewise.
	(vmaxq_u8): Likewise.
	(vhsubq_u8): Likewise.
	(vhsubq_n_u8): Likewise.
	(vhaddq_u8): Likewise.
	(vhaddq_n_u8): Likewise.
	(veorq_u8): Likewise.
	(vcmpneq_n_u8): Likewise.
	(vcmphiq_u8): Likewise.
	(vcmphiq_n_u8): Likewise.
	(vcmpeqq_u8): Likewise.
	(vcmpeqq_n_u8): Likewise.
	(vcmpcsq_u8): Likewise.
	(vcmpcsq_n_u8): Likewise.
	(vcaddq_rot90_u8): Likewise.
	(vcaddq_rot270_u8): Likewise.
	(vbicq_u8): Likewise.
	(vandq_u8): Likewise.
	(vaddvq_p_u8): Likewise.
	(vaddvaq_u8): Likewise.
	(vaddq_n_u8): Likewise.
	(vabdq_u8): Likewise.
	(vshlq_r_u8): Likewise.
	(vrshlq_u8): Likewise.
	(vrshlq_n_u8): Likewise.
	(vqshlq_u8): Likewise.
	(vqshlq_r_u8): Likewise.
	(vqrshlq_u8): Likewise.
	(vqrshlq_n_u8): Likewise.
	(vminavq_s8): Likewise.
	(vminaq_s8): Likewise.
	(vmaxavq_s8): Likewise.
	(vmaxaq_s8): Likewise.
	(vbrsrq_n_u8): Likewise.
	(vshlq_n_u8): Likewise.
	(vrshrq_n_u8): Likewise.
	(vqshlq_n_u8): Likewise.
	(vcmpneq_n_s8): Likewise.
	(vcmpltq_s8): Likewise.
	(vcmpltq_n_s8): Likewise.
	(vcmpleq_s8): Likewise.
	(vcmpleq_n_s8): Likewise.
	(vcmpgtq_s8): Likewise.
	(vcmpgtq_n_s8): Likewise.
	(vcmpgeq_s8): Likewise.
	(vcmpgeq_n_s8): Likewise.
	(vcmpeqq_s8): Likewise.
	(vcmpeqq_n_s8): Likewise.
	(vqshluq_n_s8): Likewise.
	(vaddvq_p_s8): Likewise.
	(vsubq_s8): Likewise.
	(vsubq_n_s8): Likewise.
	(vshlq_r_s8): Likewise.
	(vrshlq_s8): Likewise.
	(vrshlq_n_s8): Likewise.
	(vrmulhq_s8): Likewise.
	(vrhaddq_s8): Likewise.
	(vqsubq_s8): Likewise.
	(vqsubq_n_s8): Likewise.
	(vqshlq_s8): Likewise.
	(vqshlq_r_s8): Likewise.
	(vqrshlq_s8): Likewise.
	(vqrshlq_n_s8): Likewise.
	(vqrdmulhq_s8): Likewise.
	(vqrdmulhq_n_s8): Likewise.
	(vqdmulhq_s8): Likewise.
	(vqdmulhq_n_s8): Likewise.
	(vqaddq_s8): Likewise.
	(vqaddq_n_s8): Likewise.
	(vorrq_s8): Likewise.
	(vornq_s8): Likewise.
	(vmulq_s8): Likewise.
	(vmulq_n_s8): Likewise.
	(vmulltq_int_s8): Likewise.
	(vmullbq_int_s8): Likewise.
	(vmulhq_s8): Likewise.
	(vmlsdavxq_s8): Likewise.
	(vmlsdavq_s8): Likewise.
	(vmladavxq_s8): Likewise.
	(vmladavq_s8): Likewise.
	(vminvq_s8): Likewise.
	(vminq_s8): Likewise.
	(vmaxvq_s8): Likewise.
	(vmaxq_s8): Likewise.
	(vhsubq_s8): Likewise.
	(vhsubq_n_s8): Likewise.
	(vhcaddq_rot90_s8): Likewise.
	(vhcaddq_rot270_s8): Likewise.
	(vhaddq_s8): Likewise.
	(vhaddq_n_s8): Likewise.
	(veorq_s8): Likewise.
	(vcaddq_rot90_s8): Likewise.
	(vcaddq_rot270_s8): Likewise.
	(vbrsrq_n_s8): Likewise.
	(vbicq_s8): Likewise.
	(vandq_s8): Likewise.
	(vaddvaq_s8): Likewise.
	(vaddq_n_s8): Likewise.
	(vabdq_s8): Likewise.
	(vshlq_n_s8): Likewise.
	(vrshrq_n_s8): Likewise.
	(vqshlq_n_s8): Likewise.
	(vsubq_u16): Likewise.
	(vsubq_n_u16): Likewise.
	(vrmulhq_u16): Likewise.
	(vrhaddq_u16): Likewise.
	(vqsubq_u16): Likewise.
	(vqsubq_n_u16): Likewise.
	(vqaddq_u16): Likewise.
	(vqaddq_n_u16): Likewise.
	(vorrq_u16): Likewise.
	(vornq_u16): Likewise.
	(vmulq_u16): Likewise.
	(vmulq_n_u16): Likewise.
	(vmulltq_int_u16): Likewise.
	(vmullbq_int_u16): Likewise.
	(vmulhq_u16): Likewise.
	(vmladavq_u16): Likewise.
	(vminvq_u16): Likewise.
	(vminq_u16): Likewise.
	(vmaxvq_u16): Likewise.
	(vmaxq_u16): Likewise.
	(vhsubq_u16): Likewise.
	(vhsubq_n_u16): Likewise.
	(vhaddq_u16): Likewise.
	(vhaddq_n_u16): Likewise.
	(veorq_u16): Likewise.
	(vcmpneq_n_u16): Likewise.
	(vcmphiq_u16): Likewise.
	(vcmphiq_n_u16): Likewise.
	(vcmpeqq_u16): Likewise.
	(vcmpeqq_n_u16): Likewise.
	(vcmpcsq_u16): Likewise.
	(vcmpcsq_n_u16): Likewise.
	(vcaddq_rot90_u16): Likewise.
	(vcaddq_rot270_u16): Likewise.
	(vbicq_u16): Likewise.
	(vandq_u16): Likewise.
	(vaddvq_p_u16): Likewise.
	(vaddvaq_u16): Likewise.
	(vaddq_n_u16): Likewise.
	(vabdq_u16): Likewise.
	(vshlq_r_u16): Likewise.
	(vrshlq_u16): Likewise.
	(vrshlq_n_u16): Likewise.
	(vqshlq_u16): Likewise.
	(vqshlq_r_u16): Likewise.
	(vqrshlq_u16): Likewise.
	(vqrshlq_n_u16): Likewise.
	(vminavq_s16): Likewise.
	(vminaq_s16): Likewise.
	(vmaxavq_s16): Likewise.
	(vmaxaq_s16): Likewise.
	(vbrsrq_n_u16): Likewise.
	(vshlq_n_u16): Likewise.
	(vrshrq_n_u16): Likewise.
	(vqshlq_n_u16): Likewise.
	(vcmpneq_n_s16): Likewise.
	(vcmpltq_s16): Likewise.
	(vcmpltq_n_s16): Likewise.
	(vcmpleq_s16): Likewise.
	(vcmpleq_n_s16): Likewise.
	(vcmpgtq_s16): Likewise.
	(vcmpgtq_n_s16): Likewise.
	(vcmpgeq_s16): Likewise.
	(vcmpgeq_n_s16): Likewise.
	(vcmpeqq_s16): Likewise.
	(vcmpeqq_n_s16): Likewise.
	(vqshluq_n_s16): Likewise.
	(vaddvq_p_s16): Likewise.
	(vsubq_s16): Likewise.
	(vsubq_n_s16): Likewise.
	(vshlq_r_s16): Likewise.
	(vrshlq_s16): Likewise.
	(vrshlq_n_s16): Likewise.
	(vrmulhq_s16): Likewise.
	(vrhaddq_s16): Likewise.
	(vqsubq_s16): Likewise.
	(vqsubq_n_s16): Likewise.
	(vqshlq_s16): Likewise.
	(vqshlq_r_s16): Likewise.
	(vqrshlq_s16): Likewise.
	(vqrshlq_n_s16): Likewise.
	(vqrdmulhq_s16): Likewise.
	(vqrdmulhq_n_s16): Likewise.
	(vqdmulhq_s16): Likewise.
	(vqdmulhq_n_s16): Likewise.
	(vqaddq_s16): Likewise.
	(vqaddq_n_s16): Likewise.
	(vorrq_s16): Likewise.
	(vornq_s16): Likewise.
	(vmulq_s16): Likewise.
	(vmulq_n_s16): Likewise.
	(vmulltq_int_s16): Likewise.
	(vmullbq_int_s16): Likewise.
	(vmulhq_s16): Likewise.
	(vmlsdavxq_s16): Likewise.
	(vmlsdavq_s16): Likewise.
	(vmladavxq_s16): Likewise.
	(vmladavq_s16): Likewise.
	(vminvq_s16): Likewise.
	(vminq_s16): Likewise.
	(vmaxvq_s16): Likewise.
	(vmaxq_s16): Likewise.
	(vhsubq_s16): Likewise.
	(vhsubq_n_s16): Likewise.
	(vhcaddq_rot90_s16): Likewise.
	(vhcaddq_rot270_s16): Likewise.
	(vhaddq_s16): Likewise.
	(vhaddq_n_s16): Likewise.
	(veorq_s16): Likewise.
	(vcaddq_rot90_s16): Likewise.
	(vcaddq_rot270_s16): Likewise.
	(vbrsrq_n_s16): Likewise.
	(vbicq_s16): Likewise.
	(vandq_s16): Likewise.
	(vaddvaq_s16): Likewise.
	(vaddq_n_s16): Likewise.
	(vabdq_s16): Likewise.
	(vshlq_n_s16): Likewise.
	(vrshrq_n_s16): Likewise.
	(vqshlq_n_s16): Likewise.
	(vsubq_u32): Likewise.
	(vsubq_n_u32): Likewise.
	(vrmulhq_u32): Likewise.
	(vrhaddq_u32): Likewise.
	(vqsubq_u32): Likewise.
	(vqsubq_n_u32): Likewise.
	(vqaddq_u32): Likewise.
	(vqaddq_n_u32): Likewise.
	(vorrq_u32): Likewise.
	(vornq_u32): Likewise.
	(vmulq_u32): Likewise.
	(vmulq_n_u32): Likewise.
	(vmulltq_int_u32): Likewise.
	(vmullbq_int_u32): Likewise.
	(vmulhq_u32): Likewise.
	(vmladavq_u32): Likewise.
	(vminvq_u32): Likewise.
	(vminq_u32): Likewise.
	(vmaxvq_u32): Likewise.
	(vmaxq_u32): Likewise.
	(vhsubq_u32): Likewise.
	(vhsubq_n_u32): Likewise.
	(vhaddq_u32): Likewise.
	(vhaddq_n_u32): Likewise.
	(veorq_u32): Likewise.
	(vcmpneq_n_u32): Likewise.
	(vcmphiq_u32): Likewise.
	(vcmphiq_n_u32): Likewise.
	(vcmpeqq_u32): Likewise.
	(vcmpeqq_n_u32): Likewise.
	(vcmpcsq_u32): Likewise.
	(vcmpcsq_n_u32): Likewise.
	(vcaddq_rot90_u32): Likewise.
	(vcaddq_rot270_u32): Likewise.
	(vbicq_u32): Likewise.
	(vandq_u32): Likewise.
	(vaddvq_p_u32): Likewise.
	(vaddvaq_u32): Likewise.
	(vaddq_n_u32): Likewise.
	(vabdq_u32): Likewise.
	(vshlq_r_u32): Likewise.
	(vrshlq_u32): Likewise.
	(vrshlq_n_u32): Likewise.
	(vqshlq_u32): Likewise.
	(vqshlq_r_u32): Likewise.
	(vqrshlq_u32): Likewise.
	(vqrshlq_n_u32): Likewise.
	(vminavq_s32): Likewise.
	(vminaq_s32): Likewise.
	(vmaxavq_s32): Likewise.
	(vmaxaq_s32): Likewise.
	(vbrsrq_n_u32): Likewise.
	(vshlq_n_u32): Likewise.
	(vrshrq_n_u32): Likewise.
	(vqshlq_n_u32): Likewise.
	(vcmpneq_n_s32): Likewise.
	(vcmpltq_s32): Likewise.
	(vcmpltq_n_s32): Likewise.
	(vcmpleq_s32): Likewise.
	(vcmpleq_n_s32): Likewise.
	(vcmpgtq_s32): Likewise.
	(vcmpgtq_n_s32): Likewise.
	(vcmpgeq_s32): Likewise.
	(vcmpgeq_n_s32): Likewise.
	(vcmpeqq_s32): Likewise.
	(vcmpeqq_n_s32): Likewise.
	(vqshluq_n_s32): Likewise.
	(vaddvq_p_s32): Likewise.
	(vsubq_s32): Likewise.
	(vsubq_n_s32): Likewise.
	(vshlq_r_s32): Likewise.
	(vrshlq_s32): Likewise.
	(vrshlq_n_s32): Likewise.
	(vrmulhq_s32): Likewise.
	(vrhaddq_s32): Likewise.
	(vqsubq_s32): Likewise.
	(vqsubq_n_s32): Likewise.
	(vqshlq_s32): Likewise.
	(vqshlq_r_s32): Likewise.
	(vqrshlq_s32): Likewise.
	(vqrshlq_n_s32): Likewise.
	(vqrdmulhq_s32): Likewise.
	(vqrdmulhq_n_s32): Likewise.
	(vqdmulhq_s32): Likewise.
	(vqdmulhq_n_s32): Likewise.
	(vqaddq_s32): Likewise.
	(vqaddq_n_s32): Likewise.
	(vorrq_s32): Likewise.
	(vornq_s32): Likewise.
	(vmulq_s32): Likewise.
	(vmulq_n_s32): Likewise.
	(vmulltq_int_s32): Likewise.
	(vmullbq_int_s32): Likewise.
	(vmulhq_s32): Likewise.
	(vmlsdavxq_s32): Likewise.
	(vmlsdavq_s32): Likewise.
	(vmladavxq_s32): Likewise.
	(vmladavq_s32): Likewise.
	(vminvq_s32): Likewise.
	(vminq_s32): Likewise.
	(vmaxvq_s32): Likewise.
	(vmaxq_s32): Likewise.
	(vhsubq_s32): Likewise.
	(vhsubq_n_s32): Likewise.
	(vhcaddq_rot90_s32): Likewise.
	(vhcaddq_rot270_s32): Likewise.
	(vhaddq_s32): Likewise.
	(vhaddq_n_s32): Likewise.
	(veorq_s32): Likewise.
	(vcaddq_rot90_s32): Likewise.
	(vcaddq_rot270_s32): Likewise.
	(vbrsrq_n_s32): Likewise.
	(vbicq_s32): Likewise.
	(vandq_s32): Likewise.
	(vaddvaq_s32): Likewise.
	(vaddq_n_s32): Likewise.
	(vabdq_s32): Likewise.
	(vshlq_n_s32): Likewise.
	(vrshrq_n_s32): Likewise.
	(vqshlq_n_s32): Likewise.
	(__arm_vsubq_u8): Define intrinsic.
	(__arm_vsubq_n_u8): Likewise.
	(__arm_vrmulhq_u8): Likewise.
	(__arm_vrhaddq_u8): Likewise.
	(__arm_vqsubq_u8): Likewise.
	(__arm_vqsubq_n_u8): Likewise.
	(__arm_vqaddq_u8): Likewise.
	(__arm_vqaddq_n_u8): Likewise.
	(__arm_vorrq_u8): Likewise.
	(__arm_vornq_u8): Likewise.
	(__arm_vmulq_u8): Likewise.
	(__arm_vmulq_n_u8): Likewise.
	(__arm_vmulltq_int_u8): Likewise.
	(__arm_vmullbq_int_u8): Likewise.
	(__arm_vmulhq_u8): Likewise.
	(__arm_vmladavq_u8): Likewise.
	(__arm_vminvq_u8): Likewise.
	(__arm_vminq_u8): Likewise.
	(__arm_vmaxvq_u8): Likewise.
	(__arm_vmaxq_u8): Likewise.
	(__arm_vhsubq_u8): Likewise.
	(__arm_vhsubq_n_u8): Likewise.
	(__arm_vhaddq_u8): Likewise.
	(__arm_vhaddq_n_u8): Likewise.
	(__arm_veorq_u8): Likewise.
	(__arm_vcmpneq_n_u8): Likewise.
	(__arm_vcmphiq_u8): Likewise.
	(__arm_vcmphiq_n_u8): Likewise.
	(__arm_vcmpeqq_u8): Likewise.
	(__arm_vcmpeqq_n_u8): Likewise.
	(__arm_vcmpcsq_u8): Likewise.
	(__arm_vcmpcsq_n_u8): Likewise.
	(__arm_vcaddq_rot90_u8): Likewise.
	(__arm_vcaddq_rot270_u8): Likewise.
	(__arm_vbicq_u8): Likewise.
	(__arm_vandq_u8): Likewise.
	(__arm_vaddvq_p_u8): Likewise.
	(__arm_vaddvaq_u8): Likewise.
	(__arm_vaddq_n_u8): Likewise.
	(__arm_vabdq_u8): Likewise.
	(__arm_vshlq_r_u8): Likewise.
	(__arm_vrshlq_u8): Likewise.
	(__arm_vrshlq_n_u8): Likewise.
	(__arm_vqshlq_u8): Likewise.
	(__arm_vqshlq_r_u8): Likewise.
	(__arm_vqrshlq_u8): Likewise.
	(__arm_vqrshlq_n_u8): Likewise.
	(__arm_vminavq_s8): Likewise.
	(__arm_vminaq_s8): Likewise.
	(__arm_vmaxavq_s8): Likewise.
	(__arm_vmaxaq_s8): Likewise.
	(__arm_vbrsrq_n_u8): Likewise.
	(__arm_vshlq_n_u8): Likewise.
	(__arm_vrshrq_n_u8): Likewise.
	(__arm_vqshlq_n_u8): Likewise.
	(__arm_vcmpneq_n_s8): Likewise.
	(__arm_vcmpltq_s8): Likewise.
	(__arm_vcmpltq_n_s8): Likewise.
	(__arm_vcmpleq_s8): Likewise.
	(__arm_vcmpleq_n_s8): Likewise.
	(__arm_vcmpgtq_s8): Likewise.
	(__arm_vcmpgtq_n_s8): Likewise.
	(__arm_vcmpgeq_s8): Likewise.
	(__arm_vcmpgeq_n_s8): Likewise.
	(__arm_vcmpeqq_s8): Likewise.
	(__arm_vcmpeqq_n_s8): Likewise.
	(__arm_vqshluq_n_s8): Likewise.
	(__arm_vaddvq_p_s8): Likewise.
	(__arm_vsubq_s8): Likewise.
	(__arm_vsubq_n_s8): Likewise.
	(__arm_vshlq_r_s8): Likewise.
	(__arm_vrshlq_s8): Likewise.
	(__arm_vrshlq_n_s8): Likewise.
	(__arm_vrmulhq_s8): Likewise.
	(__arm_vrhaddq_s8): Likewise.
	(__arm_vqsubq_s8): Likewise.
	(__arm_vqsubq_n_s8): Likewise.
	(__arm_vqshlq_s8): Likewise.
	(__arm_vqshlq_r_s8): Likewise.
	(__arm_vqrshlq_s8): Likewise.
	(__arm_vqrshlq_n_s8): Likewise.
	(__arm_vqrdmulhq_s8): Likewise.
	(__arm_vqrdmulhq_n_s8): Likewise.
	(__arm_vqdmulhq_s8): Likewise.
	(__arm_vqdmulhq_n_s8): Likewise.
	(__arm_vqaddq_s8): Likewise.
	(__arm_vqaddq_n_s8): Likewise.
	(__arm_vorrq_s8): Likewise.
	(__arm_vornq_s8): Likewise.
	(__arm_vmulq_s8): Likewise.
	(__arm_vmulq_n_s8): Likewise.
	(__arm_vmulltq_int_s8): Likewise.
	(__arm_vmullbq_int_s8): Likewise.
	(__arm_vmulhq_s8): Likewise.
	(__arm_vmlsdavxq_s8): Likewise.
	(__arm_vmlsdavq_s8): Likewise.
	(__arm_vmladavxq_s8): Likewise.
	(__arm_vmladavq_s8): Likewise.
	(__arm_vminvq_s8): Likewise.
	(__arm_vminq_s8): Likewise.
	(__arm_vmaxvq_s8): Likewise.
	(__arm_vmaxq_s8): Likewise.
	(__arm_vhsubq_s8): Likewise.
	(__arm_vhsubq_n_s8): Likewise.
	(__arm_vhcaddq_rot90_s8): Likewise.
	(__arm_vhcaddq_rot270_s8): Likewise.
	(__arm_vhaddq_s8): Likewise.
	(__arm_vhaddq_n_s8): Likewise.
	(__arm_veorq_s8): Likewise.
	(__arm_vcaddq_rot90_s8): Likewise.
	(__arm_vcaddq_rot270_s8): Likewise.
	(__arm_vbrsrq_n_s8): Likewise.
	(__arm_vbicq_s8): Likewise.
	(__arm_vandq_s8): Likewise.
	(__arm_vaddvaq_s8): Likewise.
	(__arm_vaddq_n_s8): Likewise.
	(__arm_vabdq_s8): Likewise.
	(__arm_vshlq_n_s8): Likewise.
	(__arm_vrshrq_n_s8): Likewise.
	(__arm_vqshlq_n_s8): Likewise.
	(__arm_vsubq_u16): Likewise.
	(__arm_vsubq_n_u16): Likewise.
	(__arm_vrmulhq_u16): Likewise.
	(__arm_vrhaddq_u16): Likewise.
	(__arm_vqsubq_u16): Likewise.
	(__arm_vqsubq_n_u16): Likewise.
	(__arm_vqaddq_u16): Likewise.
	(__arm_vqaddq_n_u16): Likewise.
	(__arm_vorrq_u16): Likewise.
	(__arm_vornq_u16): Likewise.
	(__arm_vmulq_u16): Likewise.
	(__arm_vmulq_n_u16): Likewise.
	(__arm_vmulltq_int_u16): Likewise.
	(__arm_vmullbq_int_u16): Likewise.
	(__arm_vmulhq_u16): Likewise.
	(__arm_vmladavq_u16): Likewise.
	(__arm_vminvq_u16): Likewise.
	(__arm_vminq_u16): Likewise.
	(__arm_vmaxvq_u16): Likewise.
	(__arm_vmaxq_u16): Likewise.
	(__arm_vhsubq_u16): Likewise.
	(__arm_vhsubq_n_u16): Likewise.
	(__arm_vhaddq_u16): Likewise.
	(__arm_vhaddq_n_u16): Likewise.
	(__arm_veorq_u16): Likewise.
	(__arm_vcmpneq_n_u16): Likewise.
	(__arm_vcmphiq_u16): Likewise.
	(__arm_vcmphiq_n_u16): Likewise.
	(__arm_vcmpeqq_u16): Likewise.
	(__arm_vcmpeqq_n_u16): Likewise.
	(__arm_vcmpcsq_u16): Likewise.
	(__arm_vcmpcsq_n_u16): Likewise.
	(__arm_vcaddq_rot90_u16): Likewise.
	(__arm_vcaddq_rot270_u16): Likewise.
	(__arm_vbicq_u16): Likewise.
	(__arm_vandq_u16): Likewise.
	(__arm_vaddvq_p_u16): Likewise.
	(__arm_vaddvaq_u16): Likewise.
	(__arm_vaddq_n_u16): Likewise.
	(__arm_vabdq_u16): Likewise.
	(__arm_vshlq_r_u16): Likewise.
	(__arm_vrshlq_u16): Likewise.
	(__arm_vrshlq_n_u16): Likewise.
	(__arm_vqshlq_u16): Likewise.
	(__arm_vqshlq_r_u16): Likewise.
	(__arm_vqrshlq_u16): Likewise.
	(__arm_vqrshlq_n_u16): Likewise.
	(__arm_vminavq_s16): Likewise.
	(__arm_vminaq_s16): Likewise.
	(__arm_vmaxavq_s16): Likewise.
	(__arm_vmaxaq_s16): Likewise.
	(__arm_vbrsrq_n_u16): Likewise.
	(__arm_vshlq_n_u16): Likewise.
	(__arm_vrshrq_n_u16): Likewise.
	(__arm_vqshlq_n_u16): Likewise.
	(__arm_vcmpneq_n_s16): Likewise.
	(__arm_vcmpltq_s16): Likewise.
	(__arm_vcmpltq_n_s16): Likewise.
	(__arm_vcmpleq_s16): Likewise.
	(__arm_vcmpleq_n_s16): Likewise.
	(__arm_vcmpgtq_s16): Likewise.
	(__arm_vcmpgtq_n_s16): Likewise.
	(__arm_vcmpgeq_s16): Likewise.
	(__arm_vcmpgeq_n_s16): Likewise.
	(__arm_vcmpeqq_s16): Likewise.
	(__arm_vcmpeqq_n_s16): Likewise.
	(__arm_vqshluq_n_s16): Likewise.
	(__arm_vaddvq_p_s16): Likewise.
	(__arm_vsubq_s16): Likewise.
	(__arm_vsubq_n_s16): Likewise.
	(__arm_vshlq_r_s16): Likewise.
	(__arm_vrshlq_s16): Likewise.
	(__arm_vrshlq_n_s16): Likewise.
	(__arm_vrmulhq_s16): Likewise.
	(__arm_vrhaddq_s16): Likewise.
	(__arm_vqsubq_s16): Likewise.
	(__arm_vqsubq_n_s16): Likewise.
	(__arm_vqshlq_s16): Likewise.
	(__arm_vqshlq_r_s16): Likewise.
	(__arm_vqrshlq_s16): Likewise.
	(__arm_vqrshlq_n_s16): Likewise.
	(__arm_vqrdmulhq_s16): Likewise.
	(__arm_vqrdmulhq_n_s16): Likewise.
	(__arm_vqdmulhq_s16): Likewise.
	(__arm_vqdmulhq_n_s16): Likewise.
	(__arm_vqaddq_s16): Likewise.
	(__arm_vqaddq_n_s16): Likewise.
	(__arm_vorrq_s16): Likewise.
	(__arm_vornq_s16): Likewise.
	(__arm_vmulq_s16): Likewise.
	(__arm_vmulq_n_s16): Likewise.
	(__arm_vmulltq_int_s16): Likewise.
	(__arm_vmullbq_int_s16): Likewise.
	(__arm_vmulhq_s16): Likewise.
	(__arm_vmlsdavxq_s16): Likewise.
	(__arm_vmlsdavq_s16): Likewise.
	(__arm_vmladavxq_s16): Likewise.
	(__arm_vmladavq_s16): Likewise.
	(__arm_vminvq_s16): Likewise.
	(__arm_vminq_s16): Likewise.
	(__arm_vmaxvq_s16): Likewise.
	(__arm_vmaxq_s16): Likewise.
	(__arm_vhsubq_s16): Likewise.
	(__arm_vhsubq_n_s16): Likewise.
	(__arm_vhcaddq_rot90_s16): Likewise.
	(__arm_vhcaddq_rot270_s16): Likewise.
	(__arm_vhaddq_s16): Likewise.
	(__arm_vhaddq_n_s16): Likewise.
	(__arm_veorq_s16): Likewise.
	(__arm_vcaddq_rot90_s16): Likewise.
	(__arm_vcaddq_rot270_s16): Likewise.
	(__arm_vbrsrq_n_s16): Likewise.
	(__arm_vbicq_s16): Likewise.
	(__arm_vandq_s16): Likewise.
	(__arm_vaddvaq_s16): Likewise.
	(__arm_vaddq_n_s16): Likewise.
	(__arm_vabdq_s16): Likewise.
	(__arm_vshlq_n_s16): Likewise.
	(__arm_vrshrq_n_s16): Likewise.
	(__arm_vqshlq_n_s16): Likewise.
	(__arm_vsubq_u32): Likewise.
	(__arm_vsubq_n_u32): Likewise.
	(__arm_vrmulhq_u32): Likewise.
	(__arm_vrhaddq_u32): Likewise.
	(__arm_vqsubq_u32): Likewise.
	(__arm_vqsubq_n_u32): Likewise.
	(__arm_vqaddq_u32): Likewise.
	(__arm_vqaddq_n_u32): Likewise.
	(__arm_vorrq_u32): Likewise.
	(__arm_vornq_u32): Likewise.
	(__arm_vmulq_u32): Likewise.
	(__arm_vmulq_n_u32): Likewise.
	(__arm_vmulltq_int_u32): Likewise.
	(__arm_vmullbq_int_u32): Likewise.
	(__arm_vmulhq_u32): Likewise.
	(__arm_vmladavq_u32): Likewise.
	(__arm_vminvq_u32): Likewise.
	(__arm_vminq_u32): Likewise.
	(__arm_vmaxvq_u32): Likewise.
	(__arm_vmaxq_u32): Likewise.
	(__arm_vhsubq_u32): Likewise.
	(__arm_vhsubq_n_u32): Likewise.
	(__arm_vhaddq_u32): Likewise.
	(__arm_vhaddq_n_u32): Likewise.
	(__arm_veorq_u32): Likewise.
	(__arm_vcmpneq_n_u32): Likewise.
	(__arm_vcmphiq_u32): Likewise.
	(__arm_vcmphiq_n_u32): Likewise.
	(__arm_vcmpeqq_u32): Likewise.
	(__arm_vcmpeqq_n_u32): Likewise.
	(__arm_vcmpcsq_u32): Likewise.
	(__arm_vcmpcsq_n_u32): Likewise.
	(__arm_vcaddq_rot90_u32): Likewise.
	(__arm_vcaddq_rot270_u32): Likewise.
	(__arm_vbicq_u32): Likewise.
	(__arm_vandq_u32): Likewise.
	(__arm_vaddvq_p_u32): Likewise.
	(__arm_vaddvaq_u32): Likewise.
	(__arm_vaddq_n_u32): Likewise.
	(__arm_vabdq_u32): Likewise.
	(__arm_vshlq_r_u32): Likewise.
	(__arm_vrshlq_u32): Likewise.
	(__arm_vrshlq_n_u32): Likewise.
	(__arm_vqshlq_u32): Likewise.
	(__arm_vqshlq_r_u32): Likewise.
	(__arm_vqrshlq_u32): Likewise.
	(__arm_vqrshlq_n_u32): Likewise.
	(__arm_vminavq_s32): Likewise.
	(__arm_vminaq_s32): Likewise.
	(__arm_vmaxavq_s32): Likewise.
	(__arm_vmaxaq_s32): Likewise.
	(__arm_vbrsrq_n_u32): Likewise.
	(__arm_vshlq_n_u32): Likewise.
	(__arm_vrshrq_n_u32): Likewise.
	(__arm_vqshlq_n_u32): Likewise.
	(__arm_vcmpneq_n_s32): Likewise.
	(__arm_vcmpltq_s32): Likewise.
	(__arm_vcmpltq_n_s32): Likewise.
	(__arm_vcmpleq_s32): Likewise.
	(__arm_vcmpleq_n_s32): Likewise.
	(__arm_vcmpgtq_s32): Likewise.
	(__arm_vcmpgtq_n_s32): Likewise.
	(__arm_vcmpgeq_s32): Likewise.
	(__arm_vcmpgeq_n_s32): Likewise.
	(__arm_vcmpeqq_s32): Likewise.
	(__arm_vcmpeqq_n_s32): Likewise.
	(__arm_vqshluq_n_s32): Likewise.
	(__arm_vaddvq_p_s32): Likewise.
	(__arm_vsubq_s32): Likewise.
	(__arm_vsubq_n_s32): Likewise.
	(__arm_vshlq_r_s32): Likewise.
	(__arm_vrshlq_s32): Likewise.
	(__arm_vrshlq_n_s32): Likewise.
	(__arm_vrmulhq_s32): Likewise.
	(__arm_vrhaddq_s32): Likewise.
	(__arm_vqsubq_s32): Likewise.
	(__arm_vqsubq_n_s32): Likewise.
	(__arm_vqshlq_s32): Likewise.
	(__arm_vqshlq_r_s32): Likewise.
	(__arm_vqrshlq_s32): Likewise.
	(__arm_vqrshlq_n_s32): Likewise.
	(__arm_vqrdmulhq_s32): Likewise.
	(__arm_vqrdmulhq_n_s32): Likewise.
	(__arm_vqdmulhq_s32): Likewise.
	(__arm_vqdmulhq_n_s32): Likewise.
	(__arm_vqaddq_s32): Likewise.
	(__arm_vqaddq_n_s32): Likewise.
	(__arm_vorrq_s32): Likewise.
	(__arm_vornq_s32): Likewise.
	(__arm_vmulq_s32): Likewise.
	(__arm_vmulq_n_s32): Likewise.
	(__arm_vmulltq_int_s32): Likewise.
	(__arm_vmullbq_int_s32): Likewise.
	(__arm_vmulhq_s32): Likewise.
	(__arm_vmlsdavxq_s32): Likewise.
	(__arm_vmlsdavq_s32): Likewise.
	(__arm_vmladavxq_s32): Likewise.
	(__arm_vmladavq_s32): Likewise.
	(__arm_vminvq_s32): Likewise.
	(__arm_vminq_s32): Likewise.
	(__arm_vmaxvq_s32): Likewise.
	(__arm_vmaxq_s32): Likewise.
	(__arm_vhsubq_s32): Likewise.
	(__arm_vhsubq_n_s32): Likewise.
	(__arm_vhcaddq_rot90_s32): Likewise.
	(__arm_vhcaddq_rot270_s32): Likewise.
	(__arm_vhaddq_s32): Likewise.
	(__arm_vhaddq_n_s32): Likewise.
	(__arm_veorq_s32): Likewise.
	(__arm_vcaddq_rot90_s32): Likewise.
	(__arm_vcaddq_rot270_s32): Likewise.
	(__arm_vbrsrq_n_s32): Likewise.
	(__arm_vbicq_s32): Likewise.
	(__arm_vandq_s32): Likewise.
	(__arm_vaddvaq_s32): Likewise.
	(__arm_vaddq_n_s32): Likewise.
	(__arm_vabdq_s32): Likewise.
	(__arm_vshlq_n_s32): Likewise.
	(__arm_vrshrq_n_s32): Likewise.
	(__arm_vqshlq_n_s32): Likewise.
	(vsubq): Define polymorphic variant.
	(vsubq_n): Likewise.
	(vshlq_r): Likewise.
	(vrshlq_n): Likewise.
	(vrshlq): Likewise.
	(vrmulhq): Likewise.
	(vrhaddq): Likewise.
	(vqsubq_n): Likewise.
	(vqsubq): Likewise.
	(vqshlq): Likewise.
	(vqshlq_r): Likewise.
	(vqshluq): Likewise.
	(vrshrq_n): Likewise.
	(vshlq_n): Likewise.
	(vqshluq_n): Likewise.
	(vqshlq_n): Likewise.
	(vqrshlq_n): Likewise.
	(vqrshlq): Likewise.
	(vqrdmulhq_n): Likewise.
	(vqrdmulhq): Likewise.
	(vqdmulhq_n): Likewise.
	(vqdmulhq): Likewise.
	(vqaddq_n): Likewise.
	(vqaddq): Likewise.
	(vorrq_n): Likewise.
	(vorrq): Likewise.
	(vornq): Likewise.
	(vmulq_n): Likewise.
	(vmulq): Likewise.
	(vmulltq_int): Likewise.
	(vmullbq_int): Likewise.
	(vmulhq): Likewise.
	(vminq): Likewise.
	(vminaq): Likewise.
	(vmaxq): Likewise.
	(vmaxaq): Likewise.
	(vhsubq_n): Likewise.
	(vhsubq): Likewise.
	(vhcaddq_rot90): Likewise.
	(vhcaddq_rot270): Likewise.
	(vhaddq_n): Likewise.
	(vhaddq): Likewise.
	(veorq): Likewise.
	(vcaddq_rot90): Likewise.
	(vcaddq_rot270): Likewise.
	(vbrsrq_n): Likewise.
	(vbicq_n): Likewise.
	(vbicq): Likewise.
	(vaddq): Likewise.
	(vaddq_n): Likewise.
	(vandq): Likewise.
	(vabdq): Likewise.
	* config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
	(BINOP_NONE_NONE_NONE): Likewise.
	(BINOP_NONE_NONE_UNONE): Likewise.
	(BINOP_UNONE_NONE_IMM): Likewise.
	(BINOP_UNONE_NONE_NONE): Likewise.
	(BINOP_UNONE_UNONE_IMM): Likewise.
	(BINOP_UNONE_UNONE_NONE): Likewise.
	(BINOP_UNONE_UNONE_UNONE): Likewise.
	* config/arm/constraints.md (Ra): Define constraint to check constant is
	in the range of 0 to 7.
	(Rg): Define constriant to check the constant is one among 1, 2, 4
	and 8.
	* config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
	(mve_vaddq_n_<supf>): Likewise.
	(mve_vaddvaq_<supf>): Likewise.
	(mve_vaddvq_p_<supf>): Likewise.
	(mve_vandq_<supf>): Likewise.
	(mve_vbicq_<supf>): Likewise.
	(mve_vbrsrq_n_<supf>): Likewise.
	(mve_vcaddq_rot270_<supf>): Likewise.
	(mve_vcaddq_rot90_<supf>): Likewise.
	(mve_vcmpcsq_n_u): Likewise.
	(mve_vcmpcsq_u): Likewise.
	(mve_vcmpeqq_n_<supf>): Likewise.
	(mve_vcmpeqq_<supf>): Likewise.
	(mve_vcmpgeq_n_s): Likewise.
	(mve_vcmpgeq_s): Likewise.
	(mve_vcmpgtq_n_s): Likewise.
	(mve_vcmpgtq_s): Likewise.
	(mve_vcmphiq_n_u): Likewise.
	(mve_vcmphiq_u): Likewise.
	(mve_vcmpleq_n_s): Likewise.
	(mve_vcmpleq_s): Likewise.
	(mve_vcmpltq_n_s): Likewise.
	(mve_vcmpltq_s): Likewise.
	(mve_vcmpneq_n_<supf>): Likewise.
	(mve_vddupq_n_u): Likewise.
	(mve_veorq_<supf>): Likewise.
	(mve_vhaddq_n_<supf>): Likewise.
	(mve_vhaddq_<supf>): Likewise.
	(mve_vhcaddq_rot270_s): Likewise.
	(mve_vhcaddq_rot90_s): Likewise.
	(mve_vhsubq_n_<supf>): Likewise.
	(mve_vhsubq_<supf>): Likewise.
	(mve_vidupq_n_u): Likewise.
	(mve_vmaxaq_s): Likewise.
	(mve_vmaxavq_s): Likewise.
	(mve_vmaxq_<supf>): Likewise.
	(mve_vmaxvq_<supf>): Likewise.
	(mve_vminaq_s): Likewise.
	(mve_vminavq_s): Likewise.
	(mve_vminq_<supf>): Likewise.
	(mve_vminvq_<supf>): Likewise.
	(mve_vmladavq_<supf>): Likewise.
	(mve_vmladavxq_s): Likewise.
	(mve_vmlsdavq_s): Likewise.
	(mve_vmlsdavxq_s): Likewise.
	(mve_vmulhq_<supf>): Likewise.
	(mve_vmullbq_int_<supf>): Likewise.
	(mve_vmulltq_int_<supf>): Likewise.
	(mve_vmulq_n_<supf>): Likewise.
	(mve_vmulq_<supf>): Likewise.
	(mve_vornq_<supf>): Likewise.
	(mve_vorrq_<supf>): Likewise.
	(mve_vqaddq_n_<supf>): Likewise.
	(mve_vqaddq_<supf>): Likewise.
	(mve_vqdmulhq_n_s): Likewise.
	(mve_vqdmulhq_s): Likewise.
	(mve_vqrdmulhq_n_s): Likewise.
	(mve_vqrdmulhq_s): Likewise.
	(mve_vqrshlq_n_<supf>): Likewise.
	(mve_vqrshlq_<supf>): Likewise.
	(mve_vqshlq_n_<supf>): Likewise.
	(mve_vqshlq_r_<supf>): Likewise.
	(mve_vqshlq_<supf>): Likewise.
	(mve_vqshluq_n_s): Likewise.
	(mve_vqsubq_n_<supf>): Likewise.
	(mve_vqsubq_<supf>): Likewise.
	(mve_vrhaddq_<supf>): Likewise.
	(mve_vrmulhq_<supf>): Likewise.
	(mve_vrshlq_n_<supf>): Likewise.
	(mve_vrshlq_<supf>): Likewise.
	(mve_vrshrq_n_<supf>): Likewise.
	(mve_vshlq_n_<supf>): Likewise.
	(mve_vshlq_r_<supf>): Likewise.
	(mve_vsubq_n_<supf>): Likewise.
	(mve_vsubq_<supf>): Likewise.
	* config/arm/predicates.md (mve_imm_7): Define predicate to check
	the matching constraint Ra.
	(mve_imm_selective_upto_8): Define predicate to check the matching
	constraint Rg.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabdq_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulhq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.

This patch supports following MVE ACLE intrinsics with binary operands.

vaddlvq_p_s32, vaddlvq_p_u32, vcmpneq_s8, vcmpneq_s16, vcmpneq_s32, vcmpneq_u8, vcmpneq_u16, vcmpneq_u32, vshlq_s8, vshlq_s16, vshlq_s32, vshlq_u8, vshlq_u16, vshlq_u32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
	qualifier for binary operands.
	(BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
	(BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
	(vaddlvq_p_u32): Likewise.
	(vcmpneq_s8): Likewise.
	(vcmpneq_s16): Likewise.
	(vcmpneq_s32): Likewise.
	(vcmpneq_u8): Likewise.
	(vcmpneq_u16): Likewise.
	(vcmpneq_u32): Likewise.
	(vshlq_s8): Likewise.
	(vshlq_s16): Likewise.
	(vshlq_s32): Likewise.
	(vshlq_u8): Likewise.
	(vshlq_u16): Likewise.
	(vshlq_u32): Likewise.
	(__arm_vaddlvq_p_s32): Define intrinsic.
	(__arm_vaddlvq_p_u32): Likewise.
	(__arm_vcmpneq_s8): Likewise.
	(__arm_vcmpneq_s16): Likewise.
	(__arm_vcmpneq_s32): Likewise.
	(__arm_vcmpneq_u8): Likewise.
	(__arm_vcmpneq_u16): Likewise.
	(__arm_vcmpneq_u32): Likewise.
	(__arm_vshlq_s8): Likewise.
	(__arm_vshlq_s16): Likewise.
	(__arm_vshlq_s32): Likewise.
	(__arm_vshlq_u8): Likewise.
	(__arm_vshlq_u16): Likewise.
	(__arm_vshlq_u32): Likewise.
	(vaddlvq_p): Define polymorphic variant.
	(vcmpneq): Likewise.
	(vshlq): Likewise.
	* config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
	Use it.
	(BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
	(BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
	* config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
	(mve_vcmpneq_<supf><mode>): Likewise.
	(mve_vshlq_<supf><mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: New test.
	* gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise.

This patch supports following MVE ACLE intrinsics with binary operands.

vcvtq_n_s16_f16, vcvtq_n_s32_f32, vcvtq_n_u16_f16, vcvtq_n_u32_f32, vcreateq_u8, vcreateq_u16, vcreateq_u32, vcreateq_u64, vcreateq_s8, vcreateq_s16, vcreateq_s32, vcreateq_s64, vshrq_n_s8, vshrq_n_s16, vshrq_n_s32, vshrq_n_u8, vshrq_n_u16, vshrq_n_u32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

In this patch new constraints "Rb" and "Rf" are added, which checks the constant is with in the range of 1 to 8 and 1 to 32 respectively.

Also a new predicates "mve_imm_8" and "mve_imm_32" are added, to check the the matching constraint Rb and Rf respectively.

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
	qualifier for binary operands.
	(BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
	(vcvtq_n_s32_f32): Likewise.
	(vcvtq_n_u16_f16): Likewise.
	(vcvtq_n_u32_f32): Likewise.
	(vcreateq_u8): Likewise.
	(vcreateq_u16): Likewise.
	(vcreateq_u32): Likewise.
	(vcreateq_u64): Likewise.
	(vcreateq_s8): Likewise.
	(vcreateq_s16): Likewise.
	(vcreateq_s32): Likewise.
	(vcreateq_s64): Likewise.
	(vshrq_n_s8): Likewise.
	(vshrq_n_s16): Likewise.
	(vshrq_n_s32): Likewise.
	(vshrq_n_u8): Likewise.
	(vshrq_n_u16): Likewise.
	(vshrq_n_u32): Likewise.
	(__arm_vcreateq_u8): Define intrinsic.
	(__arm_vcreateq_u16): Likewise.
	(__arm_vcreateq_u32): Likewise.
	(__arm_vcreateq_u64): Likewise.
	(__arm_vcreateq_s8): Likewise.
	(__arm_vcreateq_s16): Likewise.
	(__arm_vcreateq_s32): Likewise.
	(__arm_vcreateq_s64): Likewise.
	(__arm_vshrq_n_s8): Likewise.
	(__arm_vshrq_n_s16): Likewise.
	(__arm_vshrq_n_s32): Likewise.
	(__arm_vshrq_n_u8): Likewise.
	(__arm_vshrq_n_u16): Likewise.
	(__arm_vshrq_n_u32): Likewise.
	(__arm_vcvtq_n_s16_f16): Likewise.
	(__arm_vcvtq_n_s32_f32): Likewise.
	(__arm_vcvtq_n_u16_f16): Likewise.
	(__arm_vcvtq_n_u32_f32): Likewise.
	(vshrq_n): Define polymorphic variant.
	* config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
	Use it.
	(BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
	* config/arm/constraints.md (Rb): Define constraint to check constant is
	in the range of 1 to 8.
	(Rf): Define constraint to check constant is in the range of 1 to 32.
	* config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
	(mve_vshrq_n_<supf><mode>): Likewise.
	(mve_vcvtq_n_from_f_<supf><mode>): Likewise.
	* config/arm/predicates.md (mve_imm_8): Define predicate to check
	the matching constraint Rb.
	(mve_imm_32): Define predicate to check the matching constraint Rf.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise.

gcc/

PR c++/94197
* cp/method.c (assignable_expr): Use cp_unevaluated.
(is_xible_helper): Push a non-deferred access check for
the stub objects created by assignable_expr and constructible_expr.

testsuite/

PR c++/94197
* g++.dg/ext/pr94197.C: New.

This patch supports following MVE ACLE intrinsics with binary operand.

vsubq_n_f16, vsubq_n_f32, vbrsrq_n_f16, vbrsrq_n_f32, vcvtq_n_f16_s16, vcvtq_n_f32_s32, vcvtq_n_f16_u16, vcvtq_n_f32_u32, vcreateq_f16, vcreateq_f32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

In this patch new constraint "Rd" is added, which checks the constant is with in the range of 1 to 16.
Also a new predicate "mve_imm_16" is added, to check the the matching constraint Rd.

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
	qualifier for binary operands.
	(BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
	(BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vsubq_n_f16): Define macro.
	(vsubq_n_f32): Likewise.
	(vbrsrq_n_f16): Likewise.
	(vbrsrq_n_f32): Likewise.
	(vcvtq_n_f16_s16): Likewise.
	(vcvtq_n_f32_s32): Likewise.
	(vcvtq_n_f16_u16): Likewise.
	(vcvtq_n_f32_u32): Likewise.
	(vcreateq_f16): Likewise.
	(vcreateq_f32): Likewise.
	(__arm_vsubq_n_f16): Define intrinsic.
	(__arm_vsubq_n_f32): Likewise.
	(__arm_vbrsrq_n_f16): Likewise.
	(__arm_vbrsrq_n_f32): Likewise.
	(__arm_vcvtq_n_f16_s16): Likewise.
	(__arm_vcvtq_n_f32_s32): Likewise.
	(__arm_vcvtq_n_f16_u16): Likewise.
	(__arm_vcvtq_n_f32_u32): Likewise.
	(__arm_vcreateq_f16): Likewise.
	(__arm_vcreateq_f32): Likewise.
	(vsubq): Define polymorphic variant.
	(vbrsrq): Likewise.
	(vcvtq_n): Likewise.
	* config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
	it.
	(BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
	(BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
	* config/arm/constraints.md (Rd): Define constraint to check constant is
	in the range of 1 to 16.
	* config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
	mve_vbrsrq_n_f<mode>: Likewise.
	mve_vcvtq_n_to_f_<supf><mode>: Likewise.
	mve_vcreateq_f<mode>: Likewise.
	* config/arm/predicates.md (mve_imm_16): Define predicate to check
	the matching constraint Rd.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.

This patch supports following MVE ACLE intrinsics with unary operand.

vctp16q, vctp32q, vctp64q, vctp8q, vpnot.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

There are few conflicts in defining the machine registers, resolved by re-ordering VPR_REGNUM, APSRQ_REGNUM and APSRGE_REGNUM.

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (hi_UP): Define mode.
	* config/arm/arm.h (IS_VPR_REGNUM): Move.
	* config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
	(APSRQ_REGNUM): Modify.
	(APSRGE_REGNUM): Modify.
	* config/arm/arm_mve.h (vctp16q): Define macro.
	(vctp32q): Likewise.
	(vctp64q): Likewise.
	(vctp8q): Likewise.
	(vpnot): Likewise.
	(__arm_vctp16q): Define intrinsic.
	(__arm_vctp32q): Likewise.
	(__arm_vctp64q): Likewise.
	(__arm_vctp8q): Likewise.
	(__arm_vpnot): Likewise.
	* config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
	qualifier.
	* config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
	(mve_vpnothi): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vctp16q.c: New test.
	* gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vpnot.c: Likewise.

This patch supports following MVE ACLE intrinsics with unary operand.

vdupq_n_s8, vdupq_n_s16, vdupq_n_s32, vabsq_s8, vabsq_s16, vabsq_s32, vclsq_s8, vclsq_s16, vclsq_s32, vclzq_s8, vclzq_s16, vclzq_s32, vnegq_s8, vnegq_s16, vnegq_s32, vaddlvq_s32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vmovlbq_s8, vmovlbq_s16, vmovltq_s8, vmovltq_s16, vmvnq_s8, vmvnq_s16, vmvnq_s32, vrev16q_s8, vrev32q_s8, vrev32q_s16, vqabsq_s8, vqabsq_s16, vqabsq_s32, vqnegq_s8, vqnegq_s16, vqnegq_s32, vcvtaq_s16_f16, vcvtaq_s32_f32, vcvtnq_s16_f16, vcvtnq_s32_f32, vcvtpq_s16_f16, vcvtpq_s32_f32, vcvtmq_s16_f16, vcvtmq_s32_f32, vmvnq_u8, vmvnq_u16, vmvnq_u32, vdupq_n_u8, vdupq_n_u16, vdupq_n_u32, vclzq_u8, vclzq_u16, vclzq_u32, vaddvq_u8, vaddvq_u16, vaddvq_u32, vrev32q_u8, vrev32q_u16, vmovltq_u8, vmovltq_u16, vmovlbq_u8, vmovlbq_u16, vrev16q_u8, vaddlvq_u32, vcvtpq_u16_f16, vcvtpq_u32_f32, vcvtnq_u16_f16, vcvtmq_u16_f16, vcvtmq_u32_f32, vcvtaq_u16_f16, vcvtaq_u32_f32, vdupq_n, vabsq, vclsq, vclzq, vnegq, vaddlvq, vaddvq, vmovlbq, vmovltq, vmvnq, vrev16q, vrev32q, vqabsq, vqnegq.

A new register class "EVEN_REGS" which allows only even registers is added in this patch.

The new constraint "e" allows only reigsters of EVEN_REGS class.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
	* config/arm/arm_mve.h (vdupq_n_s8): Define macro.
	(vdupq_n_s16): Likewise.
	(vdupq_n_s32): Likewise.
	(vabsq_s8): Likewise.
	(vabsq_s16): Likewise.
	(vabsq_s32): Likewise.
	(vclsq_s8): Likewise.
	(vclsq_s16): Likewise.
	(vclsq_s32): Likewise.
	(vclzq_s8): Likewise.
	(vclzq_s16): Likewise.
	(vclzq_s32): Likewise.
	(vnegq_s8): Likewise.
	(vnegq_s16): Likewise.
	(vnegq_s32): Likewise.
	(vaddlvq_s32): Likewise.
	(vaddvq_s8): Likewise.
	(vaddvq_s16): Likewise.
	(vaddvq_s32): Likewise.
	(vmovlbq_s8): Likewise.
	(vmovlbq_s16): Likewise.
	(vmovltq_s8): Likewise.
	(vmovltq_s16): Likewise.
	(vmvnq_s8): Likewise.
	(vmvnq_s16): Likewise.
	(vmvnq_s32): Likewise.
	(vrev16q_s8): Likewise.
	(vrev32q_s8): Likewise.
	(vrev32q_s16): Likewise.
	(vqabsq_s8): Likewise.
	(vqabsq_s16): Likewise.
	(vqabsq_s32): Likewise.
	(vqnegq_s8): Likewise.
	(vqnegq_s16): Likewise.
	(vqnegq_s32): Likewise.
	(vcvtaq_s16_f16): Likewise.
	(vcvtaq_s32_f32): Likewise.
	(vcvtnq_s16_f16): Likewise.
	(vcvtnq_s32_f32): Likewise.
	(vcvtpq_s16_f16): Likewise.
	(vcvtpq_s32_f32): Likewise.
	(vcvtmq_s16_f16): Likewise.
	(vcvtmq_s32_f32): Likewise.
	(vmvnq_u8): Likewise.
	(vmvnq_u16): Likewise.
	(vmvnq_u32): Likewise.
	(vdupq_n_u8): Likewise.
	(vdupq_n_u16): Likewise.
	(vdupq_n_u32): Likewise.
	(vclzq_u8): Likewise.
	(vclzq_u16): Likewise.
	(vclzq_u32): Likewise.
	(vaddvq_u8): Likewise.
	(vaddvq_u16): Likewise.
	(vaddvq_u32): Likewise.
	(vrev32q_u8): Likewise.
	(vrev32q_u16): Likewise.
	(vmovltq_u8): Likewise.
	(vmovltq_u16): Likewise.
	(vmovlbq_u8): Likewise.
	(vmovlbq_u16): Likewise.
	(vrev16q_u8): Likewise.
	(vaddlvq_u32): Likewise.
	(vcvtpq_u16_f16): Likewise.
	(vcvtpq_u32_f32): Likewise.
	(vcvtnq_u16_f16): Likewise.
	(vcvtmq_u16_f16): Likewise.
	(vcvtmq_u32_f32): Likewise.
	(vcvtaq_u16_f16): Likewise.
	(vcvtaq_u32_f32): Likewise.
	(__arm_vdupq_n_s8): Define intrinsic.
	(__arm_vdupq_n_s16): Likewise.
	(__arm_vdupq_n_s32): Likewise.
	(__arm_vabsq_s8): Likewise.
	(__arm_vabsq_s16): Likewise.
	(__arm_vabsq_s32): Likewise.
	(__arm_vclsq_s8): Likewise.
	(__arm_vclsq_s16): Likewise.
	(__arm_vclsq_s32): Likewise.
	(__arm_vclzq_s8): Likewise.
	(__arm_vclzq_s16): Likewise.
	(__arm_vclzq_s32): Likewise.
	(__arm_vnegq_s8): Likewise.
	(__arm_vnegq_s16): Likewise.
	(__arm_vnegq_s32): Likewise.
	(__arm_vaddlvq_s32): Likewise.
	(__arm_vaddvq_s8): Likewise.
	(__arm_vaddvq_s16): Likewise.
	(__arm_vaddvq_s32): Likewise.
	(__arm_vmovlbq_s8): Likewise.
	(__arm_vmovlbq_s16): Likewise.
	(__arm_vmovltq_s8): Likewise.
	(__arm_vmovltq_s16): Likewise.
	(__arm_vmvnq_s8): Likewise.
	(__arm_vmvnq_s16): Likewise.
	(__arm_vmvnq_s32): Likewise.
	(__arm_vrev16q_s8): Likewise.
	(__arm_vrev32q_s8): Likewise.
	(__arm_vrev32q_s16): Likewise.
	(__arm_vqabsq_s8): Likewise.
	(__arm_vqabsq_s16): Likewise.
	(__arm_vqabsq_s32): Likewise.
	(__arm_vqnegq_s8): Likewise.
	(__arm_vqnegq_s16): Likewise.
	(__arm_vqnegq_s32): Likewise.
	(__arm_vmvnq_u8): Likewise.
	(__arm_vmvnq_u16): Likewise.
	(__arm_vmvnq_u32): Likewise.
	(__arm_vdupq_n_u8): Likewise.
	(__arm_vdupq_n_u16): Likewise.
	(__arm_vdupq_n_u32): Likewise.
	(__arm_vclzq_u8): Likewise.
	(__arm_vclzq_u16): Likewise.
	(__arm_vclzq_u32): Likewise.
	(__arm_vaddvq_u8): Likewise.
	(__arm_vaddvq_u16): Likewise.
	(__arm_vaddvq_u32): Likewise.
	(__arm_vrev32q_u8): Likewise.
	(__arm_vrev32q_u16): Likewise.
	(__arm_vmovltq_u8): Likewise.
	(__arm_vmovltq_u16): Likewise.
	(__arm_vmovlbq_u8): Likewise.
	(__arm_vmovlbq_u16): Likewise.
	(__arm_vrev16q_u8): Likewise.
	(__arm_vaddlvq_u32): Likewise.
	(__arm_vcvtpq_u16_f16): Likewise.
	(__arm_vcvtpq_u32_f32): Likewise.
	(__arm_vcvtnq_u16_f16): Likewise.
	(__arm_vcvtmq_u16_f16): Likewise.
	(__arm_vcvtmq_u32_f32): Likewise.
	(__arm_vcvtaq_u16_f16): Likewise.
	(__arm_vcvtaq_u32_f32): Likewise.
	(__arm_vcvtaq_s16_f16): Likewise.
	(__arm_vcvtaq_s32_f32): Likewise.
	(__arm_vcvtnq_s16_f16): Likewise.
	(__arm_vcvtnq_s32_f32): Likewise.
	(__arm_vcvtpq_s16_f16): Likewise.
	(__arm_vcvtpq_s32_f32): Likewise.
	(__arm_vcvtmq_s16_f16): Likewise.
	(__arm_vcvtmq_s32_f32): Likewise.
	(vdupq_n): Define polymorphic variant.
	(vabsq): Likewise.
	(vclsq): Likewise.
	(vclzq): Likewise.
	(vnegq): Likewise.
	(vaddlvq): Likewise.
	(vaddvq): Likewise.
	(vmovlbq): Likewise.
	(vmovltq): Likewise.
	(vmvnq): Likewise.
	(vrev16q): Likewise.
	(vrev32q): Likewise.
	(vqabsq): Likewise.
	(vqnegq): Likewise.
	* config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
	(UNOP_SNONE_NONE): Likewise.
	(UNOP_UNONE_UNONE): Likewise.
	(UNOP_UNONE_NONE): Likewise.
	* config/arm/constraints.md (e): Define new constriant to allow only
	even registers.
	* config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
	(mve_vnegq_s<mode>): Likewise.
	(mve_vmvnq_<supf><mode>): Likewise.
	(mve_vdupq_n_<supf><mode>): Likewise.
	(mve_vclzq_<supf><mode>): Likewise.
	(mve_vclsq_s<mode>): Likewise.
	(mve_vaddvq_<supf><mode>): Likewise.
	(mve_vabsq_s<mode>): Likewise.
	(mve_vrev32q_<supf><mode>): Likewise.
	(mve_vmovltq_<supf><mode>): Likewise.
	(mve_vmovlbq_<supf><mode>): Likewise.
	(mve_vcvtpq_<supf><mode>): Likewise.
	(mve_vcvtnq_<supf><mode>): Likewise.
	(mve_vcvtmq_<supf><mode>): Likewise.
	(mve_vcvtaq_<supf><mode>): Likewise.
	(mve_vrev16q_<supf>v16qi): Likewise.
	(mve_vaddlvq_<supf>v4si): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise.

In the r10-7197-gbae7b38c commit I've
noticed duplicated word in a message, which lead me to grep for those and
we have a tons of them.
I've used
grep -v 'long long\|optab optab\|template template\|double double' *.[chS] */*.[chS] *.def config/*/* 2>/dev/null | grep ' \([a-zA-Z]\+\) \1 '
Note, the command will not detect the doubled words at the start or end of
line or when one of the words is at the end of line and the next one at the
start of another one.
Some of it is fairly obvious, e.g. all the "the the" cases which is
something I've posted and committed patch for already e.g. in 2016,
other cases are often valid, e.g. "that that" seems to look mostly ok to me.
Some cases are quite hard to figure out, I've left out some of them from the
patch (e.g. "and and" in some cases isn't talking about bitwise/logical and
and so looks incorrect, but in other cases it is talking about those
operations).
In most cases the right solution seems to be to remove one of the duplicated
words, but not always.

I think most important are the ones with user visible messages (in the patch
3 of the first 4 hunks), the rest is just comments (and internal
documentation; for that see the doc/tm.texi changes).

2020-03-17  Jakub Jelinek  <jakub@redhat.com>

	* lra-spills.c (remove_pseudos): Fix up duplicated word issue in
	a dump message.
	* tree-sra.c (create_access_replacement): Fix up duplicated word issue
	in a comment.
	* read-rtl-function.c (find_param_by_name,
	function_reader::parse_enum_value, function_reader::get_insn_by_uid):
	Likewise.
	* spellcheck.c (get_edit_distance_cutoff): Likewise.
	* tree-data-ref.c (create_ifn_alias_checks): Likewise.
	* tree.def (SWITCH_EXPR): Likewise.
	* selftest.c (assert_str_contains): Likewise.
	* ipa-param-manipulation.h (class ipa_param_body_adjustments):
	Likewise.
	* tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
	* tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
	* langhooks.h (struct lang_hooks_for_decls): Likewise.
	* ipa-prop.h (struct ipa_param_descriptor): Likewise.
	* tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
	Likewise.
	* tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
	* tree-ssa-reassoc.c (reassociate_bb): Likewise.
	* tree.c (component_ref_size): Likewise.
	* hsa-common.c (hsa_init_compilation_unit_data): Likewise.
	* gimple-ssa-sprintf.c (get_string_length, format_string,
	format_directive): Likewise.
	* omp-grid.c (grid_process_kernel_body_copy): Likewise.
	* input.c (string_concat_db::get_string_concatenation,
	test_lexer_string_locations_ucn4): Likewise.
	* cfgexpand.c (pass_expand::execute): Likewise.
	* gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
	maybe_diag_overlap): Likewise.
	* rtl.c (RTX_CODE_HWINT_P_1): Likewise.
	* shrink-wrap.c (spread_components): Likewise.
	* tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
	Likewise.
	* tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
	Likewise.
	* dwarf2out.c (dwarf2out_early_finish): Likewise.
	* gimple-ssa-store-merging.c: Likewise.
	* ira-costs.c (record_operand_costs): Likewise.
	* tree-vect-loop.c (vectorizable_reduction): Likewise.
	* target.def (dispatch): Likewise.
	(validate_dims, gen_ccmp_first): Fix up duplicated word issue
	in documentation text.
	* doc/tm.texi: Regenerated.
	* config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
	duplicated word issue in a comment.
	* config/i386/i386.c (ix86_test_loading_unspec): Likewise.
	* config/i386/i386-features.c (remove_partial_avx_dependency):
	Likewise.
	* config/msp430/msp430.c (msp430_select_section): Likewise.
	* config/gcn/gcn-run.c (load_image): Likewise.
	* config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
	* config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
	* config/aarch64/falkor-tag-collision-avoidance.c
	(single_dest_per_chain): Likewise.
	* config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
	* config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
	* config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
	* config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
	Likewise.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
	* config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
	* config/rs6000/rs6000-logue.c
	(rs6000_emit_probe_stack_range_stack_clash): Likewise.
	* config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
	Fix various other issues in the comment.
c-family/
	* c-common.c (resolve_overloaded_builtin): Fix up duplicated word
	issue in a diagnostic message.
cp/
	* pt.c (tsubst): Fix up duplicated word issue in a diagnostic message.
	(lookup_template_class_1, tsubst_expr): Fix up duplicated word issue
	in a comment.
	* parser.c (cp_parser_statement, cp_parser_linkage_specification,
	cp_parser_placeholder_type_specifier,
	cp_parser_constraint_requires_parens): Likewise.
	* name-lookup.c (suggest_alternative_in_explicit_scope): Likewise.
fortran/
	* array.c (gfc_check_iter_variable): Fix up duplicated word issue
	in a comment.
	* arith.c (gfc_arith_concat): Likewise.
	* resolve.c (gfc_resolve_ref): Likewise.
	* frontend-passes.c (matmul_lhs_realloc): Likewise.
	* module.c (gfc_match_submodule, load_needed): Likewise.
	* trans-expr.c (gfc_init_se): Likewise.

This patch adds a new multilib for armv8.1-m.main+mve with hard float abi. For
armv8.1-m.main+mve soft and softfp, the v8-M multilibs will be reused.
The following mappings are also updated:
"-mfloat-abi=hard -march=armv8.1-m.main+mve.fp -> armv8-m.main+fp/hard"
"-mfloat-abi=softfp -march=armv8.1-m.main+mve.fp -> armv8-m.main+fp/softfp"
"-mfloat-abi=soft -march=armv8.1-m.main+mve.fp -> armv8-m.main/nofp"
gcc/ChangeLog:

2020-03-17  Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/arm/t-rmprofile: create new multilib for
	armv8.1-m.main+mve hard float and reuse v8-m.main ones for
	v8.1-m.main+mve .

gcc/testsuite/ChangeLog:

2020-03-17  Mihail Ionescu  <mihail.ionescu@arm.com>

	* gcc.target/arm/multilib.exp: Add new v8.1-M entry.

libgcc/ChangLog:

2020-03-17  Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/arm/t-arm: Do not compile cmse_nonsecure_call.S for v8.1-m.

As I said already yesterday in another PR, I'm afraid the mixing of apples
and oranges (what we are actually computing, whether what bytes are zero or
non-zero in the native representation of EXP itself or what EXP points to)
in a single function where it performs some handling which must be specific
to one or the other case unconditionally and only from time to time
determines something based on if nbytes is 0 or not will continue to bite us
again and again.
So, this patch performs at least a partial cleanup to separate those two
cases into two functions.
In addition to the separation, the patch uses e.g. ctor_for_folding so that
it does handle volatile loads properly and various other checks instead of
directly using DECL_INITIAL or does guard native_encode_expr call the way it
is guarded elsewhere (that host and target byte sizes are expected).

I've left other issues I found as is for now, like the *allnonnul being IMHO
wrongly computed (if we don't know anything about the bytes, such as if
_1 = MEM[s_2(D)];
MEM[whatever] = _1;
where nothing really is known about strlen(s) etc., the code right now
clears *nulterm and *allnul, but keeps *allnonnull set), but the callers
seem to never use that value for anything (so the question is why is it
computed and how exactly should it be defined).  Another thing I find quite
weird is the distinction between count_nonzero_bytes failing (return false)
and when it succeeds, but sets values to a don't know state (the warning is
only issued if it succeeds), plus what lenrange[2] is for.  The size of the
store should be visible already from the store statement.  Also the looking
at the type of the MEM_REF first operand to determine if it is is_char_store
is really weird, because both in user code and through sccvn where pointer
conversions are useless the type of the MEM_REF operand doesn't have to have
anything to do with what the code actually does.

2020-03-17  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/94015
	* tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
	function where EXP is address of the bytes being stored rather than
	the bytes themselves into count_nonzero_bytes_addr.  Punt on zero
	sized MEM_REF.  Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
	Use ctor_for_folding instead of looking at DECL_INITIAL.  Punt before
	calling native_encode_expr if host or target doesn't have 8-bit
	chars.  Formatting fixes.
	(count_nonzero_bytes_addr): New function.

	* gcc.dg/pr94015.c: New test.

This patch supports following MVE ACLE intrinsics with unary operand.

vmvnq_n_s16, vmvnq_n_s32, vrev64q_s8, vrev64q_s16, vrev64q_s32, vcvtq_s16_f16, vcvtq_s32_f32, vrev64q_u8, vrev64q_u16, vrev64q_u32, vmvnq_n_u16, vmvnq_n_u32, vcvtq_u16_f16, vcvtq_u32_f32, vrev64q.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
	(UNOP_SNONE_NONE_QUALIFIERS): Likewise.
	(UNOP_SNONE_IMM_QUALIFIERS): Likewise.
	(UNOP_UNONE_NONE_QUALIFIERS): Likewise.
	(UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
	(UNOP_UNONE_IMM_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
	(vmvnq_n_s32): Likewise.
	(vrev64q_s8): Likewise.
	(vrev64q_s16): Likewise.
	(vrev64q_s32): Likewise.
	(vcvtq_s16_f16): Likewise.
	(vcvtq_s32_f32): Likewise.
	(vrev64q_u8): Likewise.
	(vrev64q_u16): Likewise.
	(vrev64q_u32): Likewise.
	(vmvnq_n_u16): Likewise.
	(vmvnq_n_u32): Likewise.
	(vcvtq_u16_f16): Likewise.
	(vcvtq_u32_f32): Likewise.
	(__arm_vmvnq_n_s16): Define intrinsic.
	(__arm_vmvnq_n_s32): Likewise.
	(__arm_vrev64q_s8): Likewise.
	(__arm_vrev64q_s16): Likewise.
	(__arm_vrev64q_s32): Likewise.
	(__arm_vrev64q_u8): Likewise.
	(__arm_vrev64q_u16): Likewise.
	(__arm_vrev64q_u32): Likewise.
	(__arm_vmvnq_n_u16): Likewise.
	(__arm_vmvnq_n_u32): Likewise.
	(__arm_vcvtq_s16_f16): Likewise.
	(__arm_vcvtq_s32_f32): Likewise.
	(__arm_vcvtq_u16_f16): Likewise.
	(__arm_vcvtq_u32_f32): Likewise.
	(vrev64q): Define polymorphic variant.
	* config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
	(UNOP_SNONE_NONE): Likewise.
	(UNOP_SNONE_IMM): Likewise.
	(UNOP_UNONE_UNONE): Likewise.
	(UNOP_UNONE_NONE): Likewise.
	(UNOP_UNONE_IMM): Likewise.
	* config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
	(mve_vcvtq_from_f_<supf><mode>): Likewise.
	(mve_vmvnq_n_<supf><mode>): Likewise.

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise.

This patch supports MVE ACLE intrinsics vcvtq_f16_s16, vcvtq_f32_s32, vcvtq_f16_u16, vcvtq_f32_u32n vrndxq_f16, vrndxq_f32, vrndq_f16, vrndq_f32, vrndpq_f16, vrndpq_f32, vrndnq_f16, vrndnq_f32, vrndmq_f16, vrndmq_f32, vrndaq_f16, vrndaq_f32, vrev64q_f16, vrev64q_f32, vnegq_f16, vnegq_f32, vdupq_n_f16, vdupq_n_f32, vabsq_f16, vabsq_f32, vrev32q_f16, vcvttq_f32_f16, vcvtbq_f32_f16.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
	(UNOP_NONE_SNONE_QUALIFIERS): Likewise.
	(UNOP_NONE_UNONE_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vrndxq_f16): Define macro.
	(vrndxq_f32): Likewise.
	(vrndq_f16) Likewise.
	(vrndq_f32): Likewise.
	(vrndpq_f16): Likewise.
	(vrndpq_f32): Likewise.
	(vrndnq_f16): Likewise.
	(vrndnq_f32): Likewise.
	(vrndmq_f16): Likewise.
	(vrndmq_f32): Likewise.
	(vrndaq_f16): Likewise.
	(vrndaq_f32): Likewise.
	(vrev64q_f16): Likewise.
	(vrev64q_f32): Likewise.
	(vnegq_f16): Likewise.
	(vnegq_f32): Likewise.
	(vdupq_n_f16): Likewise.
	(vdupq_n_f32): Likewise.
	(vabsq_f16): Likewise.
	(vabsq_f32): Likewise.
	(vrev32q_f16): Likewise.
	(vcvttq_f32_f16): Likewise.
	(vcvtbq_f32_f16): Likewise.
	(vcvtq_f16_s16): Likewise.
	(vcvtq_f32_s32): Likewise.
	(vcvtq_f16_u16): Likewise.
	(vcvtq_f32_u32): Likewise.
	(__arm_vrndxq_f16): Define intrinsic.
	(__arm_vrndxq_f32): Likewise.
	(__arm_vrndq_f16): Likewise.
	(__arm_vrndq_f32): Likewise.
	(__arm_vrndpq_f16): Likewise.
	(__arm_vrndpq_f32): Likewise.
	(__arm_vrndnq_f16): Likewise.
	(__arm_vrndnq_f32): Likewise.
	(__arm_vrndmq_f16): Likewise.
	(__arm_vrndmq_f32): Likewise.
	(__arm_vrndaq_f16): Likewise.
	(__arm_vrndaq_f32): Likewise.
	(__arm_vrev64q_f16): Likewise.
	(__arm_vrev64q_f32): Likewise.
	(__arm_vnegq_f16): Likewise.
	(__arm_vnegq_f32): Likewise.
	(__arm_vdupq_n_f16): Likewise.
	(__arm_vdupq_n_f32): Likewise.
	(__arm_vabsq_f16): Likewise.
	(__arm_vabsq_f32): Likewise.
	(__arm_vrev32q_f16): Likewise.
	(__arm_vcvttq_f32_f16): Likewise.
	(__arm_vcvtbq_f32_f16): Likewise.
	(__arm_vcvtq_f16_s16): Likewise.
	(__arm_vcvtq_f32_s32): Likewise.
	(__arm_vcvtq_f16_u16): Likewise.
	(__arm_vcvtq_f32_u32): Likewise.
	(vrndxq): Define polymorphic variants.
	(vrndq): Likewise.
	(vrndpq): Likewise.
	(vrndnq): Likewise.
	(vrndmq): Likewise.
	(vrndaq): Likewise.
	(vrev64q): Likewise.
	(vnegq): Likewise.
	(vabsq): Likewise.
	(vrev32q): Likewise.
	(vcvtbq_f32): Likewise.
	(vcvttq_f32): Likewise.
	(vcvtq): Likewise.
	* config/arm/arm_mve_builtins.def (VAR2): Define.
	(VAR1): Define.
	* config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
	(mve_vrndq_f<mode>): Likewise.
	(mve_vrndpq_f<mode>): Likewise.
	(mve_vrndnq_f<mode>): Likewise.
	(mve_vrndmq_f<mode>): Likewise.
	(mve_vrndaq_f<mode>): Likewise.
	(mve_vrev64q_f<mode>): Likewise.
	(mve_vnegq_f<mode>): Likewise.
	(mve_vdupq_n_f<mode>): Likewise.
	(mve_vabsq_f<mode>): Likewise.
	(mve_vrev32q_fv8hf): Likewise.
	(mve_vcvttq_f32_f16v4sf): Likewise.
	(mve_vcvtbq_f32_f16v4sf): Likewise.
	(mve_vcvtq_to_f_<supf><mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise.

This patch supports MVE ACLE intrinsics vst4q_s8, vst4q_s16, vst4q_s32, vst4q_u8, vst4q_u16, vst4q_u32, vst4q_f16 and vst4q_f32.

In this patch arm_mve_builtins.def file is added to the source code in which the builtins for MVE ACLE intrinsics are defined using builtin qualifiers.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Mihail Ionescu  <mihail.ionescu@arm.com>
	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (CF): Define mve_builtin_data.
	(VAR1): Define.
	(ARM_BUILTIN_MVE_PATTERN_START): Define.
	(arm_init_mve_builtins): Define function.
	(arm_init_builtins): Add TARGET_HAVE_MVE check.
	(arm_expand_builtin_1): Check the range of fcode.
	(arm_expand_mve_builtin): Define function to expand MVE builtins.
	(arm_expand_builtin): Check the range of fcode.
	* config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
	types.
	(__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
	(vst4q_s8): Define macro.
	(vst4q_s16): Likewise.
	(vst4q_s32): Likewise.
	(vst4q_u8): Likewise.
	(vst4q_u16): Likewise.
	(vst4q_u32): Likewise.
	(vst4q_f16): Likewise.
	(vst4q_f32): Likewise.
	(__arm_vst4q_s8): Define inline builtin.
	(__arm_vst4q_s16): Likewise.
	(__arm_vst4q_s32): Likewise.
	(__arm_vst4q_u8): Likewise.
	(__arm_vst4q_u16): Likewise.
	(__arm_vst4q_u32): Likewise.
	(__arm_vst4q_f16): Likewise.
	(__arm_vst4q_f32): Likewise.
	(__ARM_mve_typeid): Define macro with MVE types.
	(__ARM_mve_coerce): Define macro with _Generic feature.
	(vst4q): Define polymorphic variant for different vst4q builtins.
	* config/arm/arm_mve_builtins.def: New file.
	* config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
	modes in MVE.
	* config/arm/mve.md (MVE_VLD_ST): Define iterator.
	(unspec): Define unspec.
	(mve_vst4q<mode>): Define RTL pattern.
	* config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
	modes in MVE.
	(neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
	in MVE.
	(define_split): Allow OI mode split for MVE after reload.
	(define_split): Allow XI mode split for MVE after reload.
	* config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
	(arm-builtins.o): Likewise.

2020-03-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Mihail Ionescu  <mihail.ionescu@arm.com>
	    Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vst4q_f16.c: New test.
	* gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise.

I'm getting on i686-linux
FAIL: g++.target/i386/pr94185.C  -std=gnu++98 (test for excess errors)
This is because of a diagnostic that 4294967295 is unsigned only in ISO C90.
Adding U suffix fixes it and the testcase still ICEs with unfixed gcc and
passes with current trunk.

2020-03-17  Jakub Jelinek  <jakub@redhat.com>

	PR target/94185
	* g++.target/i386/pr94185.C (l): Use 4294967295U instead of 4294967295
	to avoid FAIL with -m32 -std=c++98.

2020-03-17  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* c-typeck.c (process_init_element): Handle constructor_type with
	type size represented by POLY_INT_CST.

	gcc/testsuite/
	* gcc.target/aarch64/sve/acle/general-c/sizeless-1.c: Remove
	superfluous dg-error.
	* gcc.target/aarch64/sve/acle/general-c/sizeless-2.c: Likewise.

The gcc.dg/pr68785.c test which contains:
int
foo (void)
{
  return *(int *) "";
}
has UB in the program if it is ever called, but causes UB in the compiler
as well as at least in theory non-reproduceable code generation.
The problem is that nbytes is in this case 4, prep is the
TREE_STRING_POINTER of a "" string literal with TREE_STRING_LENGTH of 1 and
we do:
4890              for (const char *p = prep; p != prep + nbytes; ++p)
4891                if (*p)
4892                  {
4893                    *allnul = false;
4894                    break;
4895                  }
and so read the bytes after the STRING_CST payload, which can be random.
I think we should just punt in this case.

2020-03-17  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/94187
	* tree-ssa-strlen.c (count_nonzero_bytes): Punt if
	nchars - offset < nbytes.

The following testcase FAILs with -O2 -fcompare-debug, but the reason isn't
that we'd emit different code based on -g or non-debug, but rather that
we emit different code depending on whether -w is used or not (or e.g.
-Wno-stringop-overflow or whether some other pass emitted some other warning
already on the call).

Code generation shouldn't depend on whether we emit a warning or not if at
all possible.

The following patch punts (i.e. doesn't optimize the strnlen call to a
constant value) if we would emit the warning if it was enabled.
In the PR there is an alternate patch which does optimize the strnlen call
no matter if we emit the warning or not, though I think I prefer the version
below, e.g. the strnlen call might be crossing field boundaries, which is in
strict reading undefined, but I'd be afraid people do that in the real
world programs.

2020-03-17  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/94189
	* builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
	emit a warning if it was enabled and don't depend on TREE_NO_WARNING
	for code-generation.

	* gcc.dg/pr94189.c: New test.