[ARM][GCC][2/2x]: MVE intrinsics with binary operands.

This patch supports following MVE ACLE intrinsics with binary operands.

vcvtq_n_s16_f16, vcvtq_n_s32_f32, vcvtq_n_u16_f16, vcvtq_n_u32_f32, vcreateq_u8, vcreateq_u16, vcreateq_u32, vcreateq_u64, vcreateq_s8, vcreateq_s16, vcreateq_s32, vcreateq_s64, vshrq_n_s8, vshrq_n_s16, vshrq_n_s32, vshrq_n_u8, vshrq_n_u16, vshrq_n_u32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

In this patch new constraints "Rb" and "Rf" are added, which checks the constant is with in the range of 1 to 8 and 1 to 32 respectively.

Also a new predicates "mve_imm_8" and "mve_imm_32" are added, to check the the matching constraint Rb and Rf respectively.

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
	qualifier for binary operands.
	(BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
	(vcvtq_n_s32_f32): Likewise.
	(vcvtq_n_u16_f16): Likewise.
	(vcvtq_n_u32_f32): Likewise.
	(vcreateq_u8): Likewise.
	(vcreateq_u16): Likewise.
	(vcreateq_u32): Likewise.
	(vcreateq_u64): Likewise.
	(vcreateq_s8): Likewise.
	(vcreateq_s16): Likewise.
	(vcreateq_s32): Likewise.
	(vcreateq_s64): Likewise.
	(vshrq_n_s8): Likewise.
	(vshrq_n_s16): Likewise.
	(vshrq_n_s32): Likewise.
	(vshrq_n_u8): Likewise.
	(vshrq_n_u16): Likewise.
	(vshrq_n_u32): Likewise.
	(__arm_vcreateq_u8): Define intrinsic.
	(__arm_vcreateq_u16): Likewise.
	(__arm_vcreateq_u32): Likewise.
	(__arm_vcreateq_u64): Likewise.
	(__arm_vcreateq_s8): Likewise.
	(__arm_vcreateq_s16): Likewise.
	(__arm_vcreateq_s32): Likewise.
	(__arm_vcreateq_s64): Likewise.
	(__arm_vshrq_n_s8): Likewise.
	(__arm_vshrq_n_s16): Likewise.
	(__arm_vshrq_n_s32): Likewise.
	(__arm_vshrq_n_u8): Likewise.
	(__arm_vshrq_n_u16): Likewise.
	(__arm_vshrq_n_u32): Likewise.
	(__arm_vcvtq_n_s16_f16): Likewise.
	(__arm_vcvtq_n_s32_f32): Likewise.
	(__arm_vcvtq_n_u16_f16): Likewise.
	(__arm_vcvtq_n_u32_f32): Likewise.
	(vshrq_n): Define polymorphic variant.
	* config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
	Use it.
	(BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
	* config/arm/constraints.md (Rb): Define constraint to check constant is
	in the range of 1 to 8.
	(Rf): Define constraint to check constant is in the range of 1 to 32.
	* config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
	(mve_vshrq_n_<supf><mode>): Likewise.
	(mve_vcvtq_n_from_f_<supf><mode>): Likewise.
	* config/arm/predicates.md (mve_imm_8): Define predicate to check
	the matching constraint Rb.
	(mve_imm_32): Define predicate to check the matching constraint Rf.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise.

gcc/ChangeLog

@@ -2,6 +2,65 @@
             Mihail Ionescu  <mihail.ionescu@arm.com>
             Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 
+	* config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
+	qualifier for binary operands.
+	(BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
+	(BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
+	* config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
+	(vcvtq_n_s32_f32): Likewise.
+	(vcvtq_n_u16_f16): Likewise.
+	(vcvtq_n_u32_f32): Likewise.
+	(vcreateq_u8): Likewise.
+	(vcreateq_u16): Likewise.
+	(vcreateq_u32): Likewise.
+	(vcreateq_u64): Likewise.
+	(vcreateq_s8): Likewise.
+	(vcreateq_s16): Likewise.
+	(vcreateq_s32): Likewise.
+	(vcreateq_s64): Likewise.
+	(vshrq_n_s8): Likewise.
+	(vshrq_n_s16): Likewise.
+	(vshrq_n_s32): Likewise.
+	(vshrq_n_u8): Likewise.
+	(vshrq_n_u16): Likewise.
+	(vshrq_n_u32): Likewise.
+	(__arm_vcreateq_u8): Define intrinsic.
+	(__arm_vcreateq_u16): Likewise.
+	(__arm_vcreateq_u32): Likewise.
+	(__arm_vcreateq_u64): Likewise.
+	(__arm_vcreateq_s8): Likewise.
+	(__arm_vcreateq_s16): Likewise.
+	(__arm_vcreateq_s32): Likewise.
+	(__arm_vcreateq_s64): Likewise.
+	(__arm_vshrq_n_s8): Likewise.
+	(__arm_vshrq_n_s16): Likewise.
+	(__arm_vshrq_n_s32): Likewise.
+	(__arm_vshrq_n_u8): Likewise.
+	(__arm_vshrq_n_u16): Likewise.
+	(__arm_vshrq_n_u32): Likewise.
+	(__arm_vcvtq_n_s16_f16): Likewise.
+	(__arm_vcvtq_n_s32_f32): Likewise.
+	(__arm_vcvtq_n_u16_f16): Likewise.
+	(__arm_vcvtq_n_u32_f32): Likewise.
+	(vshrq_n): Define polymorphic variant.
+	* config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
+	Use it.
+	(BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
+	(BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
+	* config/arm/constraints.md (Rb): Define constraint to check constant is
+	in the range of 1 to 8.
+	(Rf): Define constraint to check constant is in the range of 1 to 32.
+	* config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
+	(mve_vshrq_n_<supf><mode>): Likewise.
+	(mve_vcvtq_n_from_f_<supf><mode>): Likewise.
+	* config/arm/predicates.md (mve_imm_8): Define predicate to check
+	the matching constraint Rb.
+	(mve_imm_32): Define predicate to check the matching constraint Rf.
+
+2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+            Mihail Ionescu  <mihail.ionescu@arm.com>
+            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
 	* config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
 	qualifier for binary operands.
 	(BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.

gcc/config/arm/arm-builtins.c

@@ -397,6 +397,24 @@ arm_binop_none_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
 #define BINOP_NONE_UNONE_UNONE_QUALIFIERS \
   (arm_binop_none_unone_unone_qualifiers)
 
+static enum arm_type_qualifiers
+arm_binop_unone_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate };
+#define BINOP_UNONE_UNONE_IMM_QUALIFIERS \
+  (arm_binop_unone_unone_imm_qualifiers)
+
+static enum arm_type_qualifiers
+arm_binop_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned };
+#define BINOP_UNONE_UNONE_UNONE_QUALIFIERS \
+  (arm_binop_unone_unone_unone_qualifiers)
+
+static enum arm_type_qualifiers
+arm_binop_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_unsigned, qualifier_none, qualifier_immediate };
+#define BINOP_UNONE_NONE_IMM_QUALIFIERS \
+  (arm_binop_unone_none_imm_qualifiers)
+
 /* End of Qualifier for MVE builtins.  */
 
    /* void ([T element type] *, T, immediate).  */

gcc/config/arm/arm_mve.h

@@ -207,6 +207,24 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
 #define vcvtq_n_f32_u32(__a,  __imm6) __arm_vcvtq_n_f32_u32(__a,  __imm6)
 #define vcreateq_f16(__a, __b) __arm_vcreateq_f16(__a, __b)
 #define vcreateq_f32(__a, __b) __arm_vcreateq_f32(__a, __b)
+#define vcvtq_n_s16_f16(__a,  __imm6) __arm_vcvtq_n_s16_f16(__a,  __imm6)
+#define vcvtq_n_s32_f32(__a,  __imm6) __arm_vcvtq_n_s32_f32(__a,  __imm6)
+#define vcvtq_n_u16_f16(__a,  __imm6) __arm_vcvtq_n_u16_f16(__a,  __imm6)
+#define vcvtq_n_u32_f32(__a,  __imm6) __arm_vcvtq_n_u32_f32(__a,  __imm6)
+#define vcreateq_u8(__a, __b) __arm_vcreateq_u8(__a, __b)
+#define vcreateq_u16(__a, __b) __arm_vcreateq_u16(__a, __b)
+#define vcreateq_u32(__a, __b) __arm_vcreateq_u32(__a, __b)
+#define vcreateq_u64(__a, __b) __arm_vcreateq_u64(__a, __b)
+#define vcreateq_s8(__a, __b) __arm_vcreateq_s8(__a, __b)
+#define vcreateq_s16(__a, __b) __arm_vcreateq_s16(__a, __b)
+#define vcreateq_s32(__a, __b) __arm_vcreateq_s32(__a, __b)
+#define vcreateq_s64(__a, __b) __arm_vcreateq_s64(__a, __b)
+#define vshrq_n_s8(__a,  __imm) __arm_vshrq_n_s8(__a,  __imm)
+#define vshrq_n_s16(__a,  __imm) __arm_vshrq_n_s16(__a,  __imm)
+#define vshrq_n_s32(__a,  __imm) __arm_vshrq_n_s32(__a,  __imm)
+#define vshrq_n_u8(__a,  __imm) __arm_vshrq_n_u8(__a,  __imm)
+#define vshrq_n_u16(__a,  __imm) __arm_vshrq_n_u16(__a,  __imm)
+#define vshrq_n_u32(__a,  __imm) __arm_vshrq_n_u32(__a,  __imm)
 #endif
 
 __extension__ extern __inline void
@@ -753,6 +771,104 @@ __arm_vpnot (mve_pred16_t __a)
   return __builtin_mve_vpnothi (__a);
 }
 
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_u8 (uint64_t __a, uint64_t __b)
+{
+  return __builtin_mve_vcreateq_uv16qi (__a, __b);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_u16 (uint64_t __a, uint64_t __b)
+{
+  return __builtin_mve_vcreateq_uv8hi (__a, __b);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_u32 (uint64_t __a, uint64_t __b)
+{
+  return __builtin_mve_vcreateq_uv4si (__a, __b);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_u64 (uint64_t __a, uint64_t __b)
+{
+  return __builtin_mve_vcreateq_uv2di (__a, __b);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_s8 (uint64_t __a, uint64_t __b)
+{
+  return __builtin_mve_vcreateq_sv16qi (__a, __b);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_s16 (uint64_t __a, uint64_t __b)
+{
+  return __builtin_mve_vcreateq_sv8hi (__a, __b);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_s32 (uint64_t __a, uint64_t __b)
+{
+  return __builtin_mve_vcreateq_sv4si (__a, __b);
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_s64 (uint64_t __a, uint64_t __b)
+{
+  return __builtin_mve_vcreateq_sv2di (__a, __b);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_n_s8 (int8x16_t __a, const int __imm)
+{
+  return __builtin_mve_vshrq_n_sv16qi (__a, __imm);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_n_s16 (int16x8_t __a, const int __imm)
+{
+  return __builtin_mve_vshrq_n_sv8hi (__a, __imm);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_n_s32 (int32x4_t __a, const int __imm)
+{
+  return __builtin_mve_vshrq_n_sv4si (__a, __imm);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_n_u8 (uint8x16_t __a, const int __imm)
+{
+  return __builtin_mve_vshrq_n_uv16qi (__a, __imm);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_n_u16 (uint16x8_t __a, const int __imm)
+{
+  return __builtin_mve_vshrq_n_uv8hi (__a, __imm);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_n_u32 (uint32x4_t __a, const int __imm)
+{
+  return __builtin_mve_vshrq_n_uv4si (__a, __imm);
+}
+
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
 __extension__ extern __inline void
@@ -1165,6 +1281,34 @@ __arm_vcreateq_f32 (uint64_t __a, uint64_t __b)
   return __builtin_mve_vcreateq_fv4sf (__a, __b);
 }
 
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6)
+{
+  return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6)
+{
+  return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6)
+{
+  return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6)
+{
+  return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6);
+}
+
 #endif
 
 enum {
@@ -1677,6 +1821,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));})
 
+#define vshrq(p0,p1) __arm_vshrq(p0,p1)
+#define __arm_vshrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+  int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \
+  int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), p1), \
+  int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), p1), \
+  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), p1), \
+  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1), \
+  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1));})
+
 #endif /* MVE Floating point.  */
 
 #ifdef __cplusplus

gcc/config/arm/arm_mve_builtins.def

@@ -6,7 +6,7 @@
 
     GCC is free software; you can redistribute it and/or modify it
     under the terms of the GNU General Public License as published
-    by the Free Software Foundation; either version 3, or  (at your
+    by the Free Software Foundation; either version 3, or   (at your
     option) any later version.
 
     GCC is distributed in the hope that it will be useful, but WITHOUT
@@ -81,3 +81,9 @@ VAR2 (BINOP_NONE_NONE_NONE, vbrsrq_n_f, v8hf, v4sf)
 VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_to_f_s, v8hf, v4sf)
 VAR2 (BINOP_NONE_UNONE_IMM, vcvtq_n_to_f_u, v8hf, v4sf)
 VAR2 (BINOP_NONE_UNONE_UNONE, vcreateq_f, v8hf, v4sf)
+VAR2 (BINOP_UNONE_NONE_IMM, vcvtq_n_from_f_u, v8hi, v4si)
+VAR2 (BINOP_NONE_NONE_IMM, vcvtq_n_from_f_s, v8hi, v4si)
+VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di)
+VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di)
+VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si)
+VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si)

gcc/config/arm/constraints.md

@@ -34,7 +34,7 @@
 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
 ;;			 Dt, Dp, Dz, Tu
 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
-;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd
+;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb
 ;; in all states: Pf, Pg
 
 ;; The following memory constraints have been used:
@@ -58,6 +58,16 @@
   (and (match_code "const_int")
        (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 16")))
 
+(define_constraint "Rb"
+  "@internal In Thumb-2 state a constant in range 1 to 8"
+  (and (match_code "const_int")
+       (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 8")))
+
+(define_constraint "Rf"
+  "@internal In Thumb-2 state a constant in range 1 to 32"
+  (and (match_code "const_int")
+       (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 32")))
+
 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  "The VFP registers @code{s0}-@code{s31}.")
 

gcc/config/arm/mve.md

@@ -22,6 +22,7 @@
 (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
 (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
 (define_mode_iterator MVE_0 [V8HF V4SF])
+(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
 (define_mode_iterator MVE_3 [V16QI V8HI])
 (define_mode_iterator MVE_2 [V16QI V8HI V4SI])
 (define_mode_iterator MVE_5 [V8HI V4SI])
@@ -38,7 +39,8 @@
 			 VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
 			 VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
 			 VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
-			 VSUBQ_N_F])
+			 VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
+			 VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
 
 (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
 			    (V8HF "V8HI") (V4SF "V4SI")])
@@ -55,10 +57,16 @@
 		       (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
 		       (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
 		       (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
-		       (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")])
+		       (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
+		       (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
+		       (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s")
+		       (VCVTQ_N_FROM_F_U "u")])
 
 (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
 			(VCTP64Q "64")])
+(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
+			     (V4SI "mve_imm_32")])
+(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")])
 
 (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
 (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
@@ -79,6 +87,9 @@
 (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
 (define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
 (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
+(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
+(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
+(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
 
 (define_insn "*mve_mov<mode>"
   [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
@@ -750,3 +761,48 @@
   "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
+
+;;
+;; [vcreateq_u, vcreateq_s])
+;;
+(define_insn "mve_vcreateq_<supf><mode>"
+  [
+   (set (match_operand:MVE_1 0 "s_register_operand" "=w")
+	(unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
+		       (match_operand:DI 2 "s_register_operand" "r")]
+	 VCREATEQ))
+  ]
+  "TARGET_HAVE_MVE"
+  "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
+  [(set_attr "type" "mve_move")
+   (set_attr "length""8")])
+
+;;
+;; [vshrq_n_s, vshrq_n_u])
+;;
+(define_insn "mve_vshrq_n_<supf><mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
+	 VSHRQ_N))
+  ]
+  "TARGET_HAVE_MVE"
+  "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
+  [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
+;;
+(define_insn "mve_vcvtq_n_from_f_<supf><mode>"
+  [
+   (set (match_operand:MVE_5 0 "s_register_operand" "=w")
+	(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
+		       (match_operand:SI 2 "mve_imm_16" "Rd")]
+	 VCVTQ_N_FROM_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+  "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
+  [(set_attr "type" "mve_move")
+])

gcc/config/arm/predicates.md

@@ -35,6 +35,14 @@
 (define_predicate "mve_imm_16"
   (match_test "satisfies_constraint_Rd (op)"))
 
+;; True for immediates in the range of 1 to 8 for MVE.
+(define_predicate "mve_imm_8"
+  (match_test "satisfies_constraint_Rb (op)"))
+
+;; True for immediates in the range of 1 to 32 for MVE.
+(define_predicate "mve_imm_32"
+  (match_test "satisfies_constraint_Rf (op)"))
+
 ; Predicate for stack protector guard's address in
 ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns
 (define_predicate "guard_addr_operand"

gcc/testsuite/ChangeLog

@@ -2,6 +2,29 @@
             Mihail Ionescu  <mihail.ionescu@arm.com>
             Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 
+	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: New test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise.
+
+2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+            Mihail Ionescu  <mihail.ionescu@arm.com>
+            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
 	* gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: New test.
 	* gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise.
 	* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise.

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (uint64_t a, uint64_t b)
+{
+  return vcreateq_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmov"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (uint64_t a, uint64_t b)
+{
+  return vcreateq_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmov"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64x2_t
+foo (uint64_t a, uint64_t b)
+{
+  return vcreateq_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmov"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (uint64_t a, uint64_t b)
+{
+  return vcreateq_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmov"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint64_t a, uint64_t b)
+{
+  return vcreateq_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmov"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint64_t a, uint64_t b)
+{
+  return vcreateq_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmov"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64x2_t
+foo (uint64_t a, uint64_t b)
+{
+  return vcreateq_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmov"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint64_t a, uint64_t b)
+{
+  return vcreateq_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmov"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (float16x8_t a)
+{
+  return vcvtq_n_s16_f16 (a, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt.s16.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (float32x4_t a)
+{
+  return vcvtq_n_s32_f32 (a, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt.s32.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (float16x8_t a)
+{
+  return vcvtq_n_u16_f16 (a, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt.u16.f16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (float32x4_t a)
+{
+  return vcvtq_n_u32_f32 (a, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt.u32.f32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a)
+{
+  return vshrq_n_s16 (a, 16);
+}
+
+/* { dg-final { scan-assembler "vshr.s16"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a)
+{
+  return vshrq (a, 16);
+}
+
+/* { dg-final { scan-assembler "vshr.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a)
+{
+  return vshrq_n_s32 (a, 32);
+}
+
+/* { dg-final { scan-assembler "vshr.s32"  }  } */
+
+int32x4_t
+foo1 (int32x4_t a)
+{
+  return vshrq (a, 32);
+}
+
+/* { dg-final { scan-assembler "vshr.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a)
+{
+  return vshrq_n_s8 (a, 8);
+}
+
+/* { dg-final { scan-assembler "vshr.s8"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a)
+{
+  return vshrq (a, 8);
+}
+
+/* { dg-final { scan-assembler "vshr.s8"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a)
+{
+  return vshrq_n_u16 (a, 16);
+}
+
+/* { dg-final { scan-assembler "vshr.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a)
+{
+  return vshrq (a, 16);
+}
+
+/* { dg-final { scan-assembler "vshr.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a)
+{
+  return vshrq_n_u32 (a, 32);
+}
+
+/* { dg-final { scan-assembler "vshr.u32"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t a)
+{
+  return vshrq (a, 32);
+}
+
+/* { dg-final { scan-assembler "vshr.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a)
+{
+  return vshrq_n_u8 (a, 8);
+}
+
+/* { dg-final { scan-assembler "vshr.u8"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a)
+{
+  return vshrq (a, 8);
+}
+
+/* { dg-final { scan-assembler "vshr.u8"  }  } */