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Commit cb26919c by Richard Sandiford
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aarch64: Treat p12-p15 as call-preserved in SVE PCS functions 

Due to a stupid mistake that I can't really explain, I'd got the
treatment of p12-p15 mixed up when adding support for the SVE PCS.
The registers are supposed to be call-preserved rather than
call-clobbered.

The fix is simple, but it has quite a big effect on the PCS tests
(as it should!).

2020-03-18  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
	call-preserved for SVE PCS functions.
	(aarch64_layout_frame): Cope with up to 12 predicate save slots.
	Optimize the case in which there are no following vector save slots.

gcc/testsuite/
	* gcc.target/aarch64/sve/acle/general/cpy_1.c: Leave gaps for in the
	check-function-bodies patterns for p15 to be saved.
	* gcc.target/aarch64/sve/pcs/args_1.c (callee_pred): Expect two
	predicates to be saved.
	* gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c: Expect p12-p15
	to be saved and restored.
	* gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_4_be.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_4_le.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_5_be.c: Likewise.
	* gcc.target/aarch64/sve/pcs/saves_5_le.c: Likewise.
	* gcc.target/aarch64/sve/pcs/stack_clash_1.c (test_1): Likewise.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_128.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_256.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	(test_4): Expect only 16 bytes of stack to be allocated for the
	predicate save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_512.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	(test_4): Expect only 16 bytes of stack to be allocated for the
	predicate save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	(test_4): Expect only 16 bytes of stack to be allocated for the
	predicate save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c (test_1): Expect
	p12-p15 to be saved and restored.
	(test_2): Remove p12-p15 from the clobber list.
	(test_4): Expect only 32 bytes of stack to be allocated for the
	predicate save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_256.c: Use z16 rather
	than p4 to create a vector-sized save slot.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_512.c: Likewise.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c: Likewise.
	* gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c: Likewise.
parent 4da92887
Showing with 839 additions and 636 deletions
gcc/ChangeLog
2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
call-preserved for SVE PCS functions.
(aarch64_layout_frame): Cope with up to 12 predicate save slots.
Optimize the case in which there are no following vector save slots.
2020-03-18 Richard Biener <rguenther@suse.de> 2020-03-18 Richard Biener <rguenther@suse.de>
PR middle-end/94188 PR middle-end/94188
......
gcc/config/aarch64/aarch64.c
...@@ -1425,7 +1425,7 @@ aarch64_sve_abi (void) ...@@ -1425,7 +1425,7 @@ aarch64_sve_abi (void)
= default_function_abi.full_reg_clobbers (); = default_function_abi.full_reg_clobbers ();
for (int regno = V8_REGNUM; regno <= V23_REGNUM; ++regno) for (int regno = V8_REGNUM; regno <= V23_REGNUM; ++regno)
CLEAR_HARD_REG_BIT (full_reg_clobbers, regno); CLEAR_HARD_REG_BIT (full_reg_clobbers, regno);
for (int regno = P4_REGNUM; regno <= P11_REGNUM; ++regno) for (int regno = P4_REGNUM; regno <= P15_REGNUM; ++regno)
CLEAR_HARD_REG_BIT (full_reg_clobbers, regno); CLEAR_HARD_REG_BIT (full_reg_clobbers, regno);
sve_abi.initialize (ARM_PCS_SVE, full_reg_clobbers); sve_abi.initialize (ARM_PCS_SVE, full_reg_clobbers);
} }
...@@ -6008,14 +6008,31 @@ aarch64_layout_frame (void) ...@@ -6008,14 +6008,31 @@ aarch64_layout_frame (void)
offset += BYTES_PER_SVE_PRED; offset += BYTES_PER_SVE_PRED;
} }
/* We save a maximum of 8 predicate registers, and since vector
registers are 8 times the size of a predicate register, all the
saved predicates fit within a single vector. Doing this also
rounds the offset to a 128-bit boundary. */
if (maybe_ne (offset, 0)) if (maybe_ne (offset, 0))
{ {
gcc_assert (known_le (offset, vector_save_size)); /* If we have any vector registers to save above the predicate registers,
offset = vector_save_size; the offset of the vector register save slots need to be a multiple
of the vector size. This lets us use the immediate forms of LDR/STR
(or LD1/ST1 for big-endian).
A vector register is 8 times the size of a predicate register,
and we need to save a maximum of 12 predicate registers, so the
first vector register will be at either #1, MUL VL or #2, MUL VL.
If we don't have any vector registers to save, and we know how
big the predicate save area is, we can just round it up to the
next 16-byte boundary. */
if (last_fp_reg == (int) INVALID_REGNUM && offset.is_constant ())
offset = aligned_upper_bound (offset, STACK_BOUNDARY / BITS_PER_UNIT);
else
{
if (known_le (offset, vector_save_size))
offset = vector_save_size;
else if (known_le (offset, vector_save_size * 2))
offset = vector_save_size * 2;
else
gcc_unreachable ();
}
} }
/* If we need to save any SVE vector registers, add them next. */ /* If we need to save any SVE vector registers, add them next. */
......
gcc/testsuite/ChangeLog
2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/acle/general/cpy_1.c: Leave gaps for in the
check-function-bodies patterns for p15 to be saved.
* gcc.target/aarch64/sve/pcs/args_1.c (callee_pred): Expect two
predicates to be saved.
* gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
* gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
* gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
* gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
* gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c: Expect p12-p15
to be saved and restored.
* gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_4_be.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_4_le.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_5_be.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_5_le.c: Likewise.
* gcc.target/aarch64/sve/pcs/stack_clash_1.c (test_1): Likewise.
(test_2): Remove p12-p15 from the clobber list.
* gcc.target/aarch64/sve/pcs/stack_clash_1_128.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
* gcc.target/aarch64/sve/pcs/stack_clash_1_256.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
(test_4): Expect only 16 bytes of stack to be allocated for the
predicate save slot.
* gcc.target/aarch64/sve/pcs/stack_clash_1_512.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
(test_4): Expect only 16 bytes of stack to be allocated for the
predicate save slot.
* gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
(test_4): Expect only 16 bytes of stack to be allocated for the
predicate save slot.
* gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c (test_1): Expect
p12-p15 to be saved and restored.
(test_2): Remove p12-p15 from the clobber list.
(test_4): Expect only 32 bytes of stack to be allocated for the
predicate save slot.
* gcc.target/aarch64/sve/pcs/stack_clash_2_256.c: Use z16 rather
than p4 to create a vector-sized save slot.
* gcc.target/aarch64/sve/pcs/stack_clash_2_512.c: Likewise.
* gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c: Likewise.
* gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c: Likewise.
2020-03-18 Tobias Burnus <tobias@codesourcery.com> 2020-03-18 Tobias Burnus <tobias@codesourcery.com>
* g++.dg/goacc/firstprivate-mappings-1.C: Only set DO_LONG_DOUBLE if * g++.dg/goacc/firstprivate-mappings-1.C: Only set DO_LONG_DOUBLE if
......
gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c
...@@ -10,9 +10,11 @@ extern "C" { ...@@ -10,9 +10,11 @@ extern "C" {
/* /*
** dup_x0_m: ** dup_x0_m:
** ...
** add (x[0-9]+), x0, #?1 ** add (x[0-9]+), x0, #?1
** mov (p[0-7])\.b, p15\.b ** mov (p[0-7])\.b, p15\.b
** mov z0\.d, \2/m, \1 ** mov z0\.d, \2/m, \1
** ...
** ret ** ret
*/ */
svuint64_t svuint64_t
...@@ -25,8 +27,10 @@ dup_x0_m (svuint64_t z0, uint64_t x0) ...@@ -25,8 +27,10 @@ dup_x0_m (svuint64_t z0, uint64_t x0)
/* /*
** dup_d1_z: ** dup_d1_z:
** ...
** mov (p[0-7])\.b, p15\.b ** mov (p[0-7])\.b, p15\.b
** mov z0\.d, \1/m, d1 ** mov z0\.d, \1/m, d1
** ...
** ret ** ret
*/ */
svfloat64_t svfloat64_t
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c
...@@ -6,11 +6,17 @@ ...@@ -6,11 +6,17 @@
/* /*
** callee_pred: ** callee_pred:
** addvl sp, sp, #-1
** str p[0-9]+, \[sp\]
** str p[0-9]+, \[sp, #1, mul vl\]
** ldr (p[0-9]+), \[x0\] ** ldr (p[0-9]+), \[x0\]
** ldr (p[0-9]+), \[x1\] ** ldr (p[0-9]+), \[x1\]
** brkpa (p[0-7])\.b, p0/z, p1\.b, p2\.b ** brkpa (p[0-7])\.b, p0/z, p1\.b, p2\.b
** brkpb (p[0-7])\.b, \3/z, p3\.b, \1\.b ** brkpb (p[0-7])\.b, \3/z, p3\.b, \1\.b
** brka p0\.b, \4/z, \2\.b ** brka p0\.b, \4/z, \2\.b
** ldr p[0-9]+, \[sp\]
** ldr p[0-9]+, \[sp, #1, mul vl\]
** addvl sp, sp, #1
** ret ** ret
*/ */
__SVBool_t __attribute__((noipa)) __SVBool_t __attribute__((noipa))
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** addvl sp, sp, #-17 ** addvl sp, sp, #-18
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -15,43 +15,47 @@ ...@@ -15,43 +15,47 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str p12, \[sp, #8, mul vl\]
** str p13, \[sp, #9, mul vl\]
** str p14, \[sp, #10, mul vl\]
** str p15, \[sp, #11, mul vl\]
** ptrue p1\.b, all ** ptrue p1\.b, all
** st1d z8\.d, p1, \[sp, #1, mul vl\] ** st1d z8\.d, p1, \[sp, #2, mul vl\]
** st1d z9\.d, p1, \[sp, #2, mul vl\] ** st1d z9\.d, p1, \[sp, #3, mul vl\]
** st1d z10\.d, p1, \[sp, #3, mul vl\] ** st1d z10\.d, p1, \[sp, #4, mul vl\]
** st1d z11\.d, p1, \[sp, #4, mul vl\] ** st1d z11\.d, p1, \[sp, #5, mul vl\]
** st1d z12\.d, p1, \[sp, #5, mul vl\] ** st1d z12\.d, p1, \[sp, #6, mul vl\]
** st1d z13\.d, p1, \[sp, #6, mul vl\] ** st1d z13\.d, p1, \[sp, #7, mul vl\]
** st1d z14\.d, p1, \[sp, #7, mul vl\]
** addvl x11, sp, #16 ** addvl x11, sp, #16
** st1d z15\.d, p1, \[x11, #-8, mul vl\] ** st1d z14\.d, p1, \[x11, #-8, mul vl\]
** str z16, \[sp, #9, mul vl\] ** st1d z15\.d, p1, \[x11, #-7, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z20, \[sp, #14, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z21, \[sp, #15, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, all ** ptrue p0\.b, all
** ptrue p1\.b, all ** ptrue p1\.b, all
** ld1d z8\.d, p1/z, \[sp, #1, mul vl\] ** ld1d z8\.d, p1/z, \[sp, #2, mul vl\]
** ld1d z9\.d, p1/z, \[sp, #2, mul vl\] ** ld1d z9\.d, p1/z, \[sp, #3, mul vl\]
** ld1d z10\.d, p1/z, \[sp, #3, mul vl\] ** ld1d z10\.d, p1/z, \[sp, #4, mul vl\]
** ld1d z11\.d, p1/z, \[sp, #4, mul vl\] ** ld1d z11\.d, p1/z, \[sp, #5, mul vl\]
** ld1d z12\.d, p1/z, \[sp, #5, mul vl\] ** ld1d z12\.d, p1/z, \[sp, #6, mul vl\]
** ld1d z13\.d, p1/z, \[sp, #6, mul vl\] ** ld1d z13\.d, p1/z, \[sp, #7, mul vl\]
** ld1d z14\.d, p1/z, \[sp, #7, mul vl\]
** addvl x11, sp, #16 ** addvl x11, sp, #16
** ld1d z15\.d, p1/z, \[x11, #-8, mul vl\] ** ld1d z14\.d, p1/z, \[x11, #-8, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ld1d z15\.d, p1/z, \[x11, #-7, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -60,7 +64,11 @@ ...@@ -60,7 +64,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** addvl sp, sp, #17 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** addvl sp, sp, #18
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -87,7 +95,7 @@ test_2 (void) ...@@ -87,7 +95,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** addvl sp, sp, #-17 ** addvl sp, sp, #-18
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -15,43 +15,47 @@ ...@@ -15,43 +15,47 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str p12, \[sp, #8, mul vl\]
** str p13, \[sp, #9, mul vl\]
** str p14, \[sp, #10, mul vl\]
** str p15, \[sp, #11, mul vl\]
** ptrue p1\.b, all ** ptrue p1\.b, all
** st1d z8\.d, p1, \[sp, #1, mul vl\] ** st1d z8\.d, p1, \[sp, #2, mul vl\]
** st1d z9\.d, p1, \[sp, #2, mul vl\] ** st1d z9\.d, p1, \[sp, #3, mul vl\]
** st1d z10\.d, p1, \[sp, #3, mul vl\] ** st1d z10\.d, p1, \[sp, #4, mul vl\]
** st1d z11\.d, p1, \[sp, #4, mul vl\] ** st1d z11\.d, p1, \[sp, #5, mul vl\]
** st1d z12\.d, p1, \[sp, #5, mul vl\] ** st1d z12\.d, p1, \[sp, #6, mul vl\]
** st1d z13\.d, p1, \[sp, #6, mul vl\] ** st1d z13\.d, p1, \[sp, #7, mul vl\]
** st1d z14\.d, p1, \[sp, #7, mul vl\]
** addvl x11, sp, #16 ** addvl x11, sp, #16
** st1d z15\.d, p1, \[x11, #-8, mul vl\] ** st1d z14\.d, p1, \[x11, #-8, mul vl\]
** str z16, \[sp, #9, mul vl\] ** st1d z15\.d, p1, \[x11, #-7, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z20, \[sp, #14, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z21, \[sp, #15, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, all ** ptrue p0\.b, all
** ptrue p1\.b, all ** ptrue p1\.b, all
** ld1d z8\.d, p1/z, \[sp, #1, mul vl\] ** ld1d z8\.d, p1/z, \[sp, #2, mul vl\]
** ld1d z9\.d, p1/z, \[sp, #2, mul vl\] ** ld1d z9\.d, p1/z, \[sp, #3, mul vl\]
** ld1d z10\.d, p1/z, \[sp, #3, mul vl\] ** ld1d z10\.d, p1/z, \[sp, #4, mul vl\]
** ld1d z11\.d, p1/z, \[sp, #4, mul vl\] ** ld1d z11\.d, p1/z, \[sp, #5, mul vl\]
** ld1d z12\.d, p1/z, \[sp, #5, mul vl\] ** ld1d z12\.d, p1/z, \[sp, #6, mul vl\]
** ld1d z13\.d, p1/z, \[sp, #6, mul vl\] ** ld1d z13\.d, p1/z, \[sp, #7, mul vl\]
** ld1d z14\.d, p1/z, \[sp, #7, mul vl\]
** addvl x11, sp, #16 ** addvl x11, sp, #16
** ld1d z15\.d, p1/z, \[x11, #-8, mul vl\] ** ld1d z14\.d, p1/z, \[x11, #-8, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ld1d z15\.d, p1/z, \[x11, #-7, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -60,7 +64,11 @@ ...@@ -60,7 +64,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** addvl sp, sp, #17 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** addvl sp, sp, #18
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -87,7 +95,7 @@ test_2 (void) ...@@ -87,7 +95,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** addvl sp, sp, #-17 ** addvl sp, sp, #-18
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -15,39 +15,43 @@ ...@@ -15,39 +15,43 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, all ** ptrue p0\.b, all
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -56,7 +60,11 @@ ...@@ -56,7 +60,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** addvl sp, sp, #17 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** addvl sp, sp, #18
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -83,7 +91,7 @@ test_2 (void) ...@@ -83,7 +91,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** addvl sp, sp, #-17 ** addvl sp, sp, #-18
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -15,39 +15,43 @@ ...@@ -15,39 +15,43 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, all ** ptrue p0\.b, all
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -56,7 +60,11 @@ ...@@ -56,7 +60,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** addvl sp, sp, #17 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** addvl sp, sp, #18
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -83,7 +91,7 @@ test_2 (void) ...@@ -83,7 +91,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_be.c
...@@ -14,7 +14,7 @@ void standard_callee (__SVInt8_t *); ...@@ -14,7 +14,7 @@ void standard_callee (__SVInt8_t *);
** stp x29, x30, \[sp\] ** stp x29, x30, \[sp\]
** ) ** )
** mov x29, sp ** mov x29, sp
** addvl sp, sp, #-17 ** addvl sp, sp, #-18
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -23,45 +23,49 @@ void standard_callee (__SVInt8_t *); ...@@ -23,45 +23,49 @@ void standard_callee (__SVInt8_t *);
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str p12, \[sp, #8, mul vl\]
** str p13, \[sp, #9, mul vl\]
** str p14, \[sp, #10, mul vl\]
** str p15, \[sp, #11, mul vl\]
** ptrue p0\.b, all ** ptrue p0\.b, all
** st1d z8\.d, p0, \[sp, #1, mul vl\] ** st1d z8\.d, p0, \[sp, #2, mul vl\]
** st1d z9\.d, p0, \[sp, #2, mul vl\] ** st1d z9\.d, p0, \[sp, #3, mul vl\]
** st1d z10\.d, p0, \[sp, #3, mul vl\] ** st1d z10\.d, p0, \[sp, #4, mul vl\]
** st1d z11\.d, p0, \[sp, #4, mul vl\] ** st1d z11\.d, p0, \[sp, #5, mul vl\]
** st1d z12\.d, p0, \[sp, #5, mul vl\] ** st1d z12\.d, p0, \[sp, #6, mul vl\]
** st1d z13\.d, p0, \[sp, #6, mul vl\] ** st1d z13\.d, p0, \[sp, #7, mul vl\]
** st1d z14\.d, p0, \[sp, #7, mul vl\]
** addvl x11, sp, #16 ** addvl x11, sp, #16
** st1d z15\.d, p0, \[x11, #-8, mul vl\] ** st1d z14\.d, p0, \[x11, #-8, mul vl\]
** str z16, \[sp, #9, mul vl\] ** st1d z15\.d, p0, \[x11, #-7, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z20, \[sp, #14, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z21, \[sp, #15, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z22, \[sp, #16, mul vl\]
** addvl x0, sp, #17 ** str z23, \[sp, #17, mul vl\]
** addvl x0, sp, #18
** add x0, x0, #?16 ** add x0, x0, #?16
** bl standard_callee ** bl standard_callee
** ptrue p0\.b, all ** ptrue p0\.b, all
** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] ** ld1d z8\.d, p0/z, \[sp, #2, mul vl\]
** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] ** ld1d z9\.d, p0/z, \[sp, #3, mul vl\]
** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] ** ld1d z10\.d, p0/z, \[sp, #4, mul vl\]
** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] ** ld1d z11\.d, p0/z, \[sp, #5, mul vl\]
** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] ** ld1d z12\.d, p0/z, \[sp, #6, mul vl\]
** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] ** ld1d z13\.d, p0/z, \[sp, #7, mul vl\]
** ld1d z14\.d, p0/z, \[sp, #7, mul vl\]
** addvl x11, sp, #16 ** addvl x11, sp, #16
** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] ** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -70,7 +74,11 @@ void standard_callee (__SVInt8_t *); ...@@ -70,7 +74,11 @@ void standard_callee (__SVInt8_t *);
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** addvl sp, sp, #17 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** addvl sp, sp, #18
** ( ** (
** ldp x29, x30, \[sp\], 16 ** ldp x29, x30, \[sp\], 16
** addvl sp, sp, #1 ** addvl sp, sp, #1
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_4_le.c
...@@ -14,7 +14,7 @@ void standard_callee (__SVInt8_t *); ...@@ -14,7 +14,7 @@ void standard_callee (__SVInt8_t *);
** stp x29, x30, \[sp\] ** stp x29, x30, \[sp\]
** ) ** )
** mov x29, sp ** mov x29, sp
** addvl sp, sp, #-17 ** addvl sp, sp, #-18
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -23,41 +23,45 @@ void standard_callee (__SVInt8_t *); ...@@ -23,41 +23,45 @@ void standard_callee (__SVInt8_t *);
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** addvl x0, sp, #17 ** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** addvl x0, sp, #18
** add x0, x0, #?16 ** add x0, x0, #?16
** bl standard_callee ** bl standard_callee
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -66,7 +70,11 @@ void standard_callee (__SVInt8_t *); ...@@ -66,7 +70,11 @@ void standard_callee (__SVInt8_t *);
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** addvl sp, sp, #17 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** addvl sp, sp, #18
** ( ** (
** ldp x29, x30, \[sp\], 16 ** ldp x29, x30, \[sp\], 16
** addvl sp, sp, #1 ** addvl sp, sp, #1
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_be.c
...@@ -8,40 +8,40 @@ void standard_callee (void); ...@@ -8,40 +8,40 @@ void standard_callee (void);
** calls_standard: ** calls_standard:
** stp x29, x30, \[sp, -16\]! ** stp x29, x30, \[sp, -16\]!
** mov x29, sp ** mov x29, sp
** addvl sp, sp, #-17 ** addvl sp, sp, #-18
** ptrue p0\.b, all ** ptrue p0\.b, all
** st1d z8\.d, p0, \[sp, #1, mul vl\] ** st1d z8\.d, p0, \[sp, #2, mul vl\]
** st1d z9\.d, p0, \[sp, #2, mul vl\] ** st1d z9\.d, p0, \[sp, #3, mul vl\]
** st1d z10\.d, p0, \[sp, #3, mul vl\] ** st1d z10\.d, p0, \[sp, #4, mul vl\]
** st1d z11\.d, p0, \[sp, #4, mul vl\] ** st1d z11\.d, p0, \[sp, #5, mul vl\]
** st1d z12\.d, p0, \[sp, #5, mul vl\] ** st1d z12\.d, p0, \[sp, #6, mul vl\]
** st1d z13\.d, p0, \[sp, #6, mul vl\] ** st1d z13\.d, p0, \[sp, #7, mul vl\]
** st1d z14\.d, p0, \[sp, #7, mul vl\]
** addvl x11, sp, #16 ** addvl x11, sp, #16
** st1d z15\.d, p0, \[x11, #-8, mul vl\] ** st1d z14\.d, p0, \[x11, #-8, mul vl\]
** st1d z15\.d, p0, \[x11, #-7, mul vl\]
** cbnz w0, \.L[0-9]+ ** cbnz w0, \.L[0-9]+
** ptrue p0\.b, all ** ptrue p0\.b, all
** ld1d z8\.d, p0/z, \[sp, #1, mul vl\] ** ld1d z8\.d, p0/z, \[sp, #2, mul vl\]
** ld1d z9\.d, p0/z, \[sp, #2, mul vl\] ** ld1d z9\.d, p0/z, \[sp, #3, mul vl\]
** ld1d z10\.d, p0/z, \[sp, #3, mul vl\] ** ld1d z10\.d, p0/z, \[sp, #4, mul vl\]
** ld1d z11\.d, p0/z, \[sp, #4, mul vl\] ** ld1d z11\.d, p0/z, \[sp, #5, mul vl\]
** ld1d z12\.d, p0/z, \[sp, #5, mul vl\] ** ld1d z12\.d, p0/z, \[sp, #6, mul vl\]
** ld1d z13\.d, p0/z, \[sp, #6, mul vl\] ** ld1d z13\.d, p0/z, \[sp, #7, mul vl\]
** ld1d z14\.d, p0/z, \[sp, #7, mul vl\]
** addvl x11, sp, #16 ** addvl x11, sp, #16
** ld1d z15\.d, p0/z, \[x11, #-8, mul vl\] ** ld1d z14\.d, p0/z, \[x11, #-8, mul vl\]
** addvl sp, sp, #17 ** ld1d z15\.d, p0/z, \[x11, #-7, mul vl\]
** addvl sp, sp, #18
** ldp x29, x30, \[sp\], 16 ** ldp x29, x30, \[sp\], 16
** ret ** ret
** ... ** ...
** str z16, \[sp, #9, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z23, \[sp, #17, mul vl\]
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -50,15 +50,19 @@ void standard_callee (void); ...@@ -50,15 +50,19 @@ void standard_callee (void);
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str p12, \[sp, #8, mul vl\]
** str p13, \[sp, #9, mul vl\]
** str p14, \[sp, #10, mul vl\]
** str p15, \[sp, #11, mul vl\]
** bl standard_callee ** bl standard_callee
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -67,6 +71,10 @@ void standard_callee (void); ...@@ -67,6 +71,10 @@ void standard_callee (void);
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** b \.L[0-9]+ ** b \.L[0-9]+
*/ */
void void
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_5_le.c
...@@ -8,29 +8,29 @@ void standard_callee (void); ...@@ -8,29 +8,29 @@ void standard_callee (void);
** calls_standard: ** calls_standard:
** stp x29, x30, \[sp, -16\]! ** stp x29, x30, \[sp, -16\]!
** mov x29, sp ** mov x29, sp
** addvl sp, sp, #-17 ** addvl sp, sp, #-18
** str z8, \[sp, #1, mul vl\] ** str z8, \[sp, #2, mul vl\]
** cbnz w0, \.L[0-9]+ ** cbnz w0, \.L[0-9]+
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** addvl sp, sp, #17 ** addvl sp, sp, #18
** ldp x29, x30, \[sp\], 16 ** ldp x29, x30, \[sp\], 16
** ret ** ret
** ... ** ...
** str z9, \[sp, #2, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z23, \[sp, #17, mul vl\]
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -39,22 +39,26 @@ void standard_callee (void); ...@@ -39,22 +39,26 @@ void standard_callee (void);
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str p12, \[sp, #8, mul vl\]
** str p13, \[sp, #9, mul vl\]
** str p14, \[sp, #10, mul vl\]
** str p15, \[sp, #11, mul vl\]
** bl standard_callee ** bl standard_callee
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -63,6 +67,10 @@ void standard_callee (void); ...@@ -63,6 +67,10 @@ void standard_callee (void);
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** b \.L[0-9]+ ** b \.L[0-9]+
*/ */
void void
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1.c
...@@ -6,9 +6,8 @@ ...@@ -6,9 +6,8 @@
/* /*
** test_1: ** test_1:
** cntb x12 ** cntd x12, all, mul #9
** mov x13, #?17 ** lsl x12, x12, #?4
** mul x12, x12, x13
** mov x11, sp ** mov x11, sp
** ... ** ...
** sub sp, sp, x12 ** sub sp, sp, x12
...@@ -20,39 +19,43 @@ ...@@ -20,39 +19,43 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, all ** ptrue p0\.b, all
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -61,7 +64,11 @@ ...@@ -61,7 +64,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** addvl sp, sp, #17 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** addvl sp, sp, #18
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -88,7 +95,7 @@ test_2 (void) ...@@ -88,7 +95,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_1024.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** sub sp, sp, #2176 ** sub sp, sp, #2304
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -15,39 +15,43 @@ ...@@ -15,39 +15,43 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -56,7 +60,11 @@ ...@@ -56,7 +60,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** add sp, sp, #?2176 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** add sp, sp, #?2304
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -83,7 +91,7 @@ test_2 (void) ...@@ -83,7 +91,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -121,11 +129,11 @@ test_3 (void) ...@@ -121,11 +129,11 @@ test_3 (void)
/* /*
** test_4: ** test_4:
** sub sp, sp, #128 ** sub sp, sp, #16
** str p4, \[sp\] ** str p4, \[sp\]
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** add sp, sp, #?128 ** add sp, sp, #?16
** ret ** ret
*/ */
svbool_t svbool_t
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_128.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** sub sp, sp, #272 ** sub sp, sp, #288
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -15,39 +15,43 @@ ...@@ -15,39 +15,43 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, vl16 ** ptrue p0\.b, vl16
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -56,7 +60,11 @@ ...@@ -56,7 +60,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** add sp, sp, #?272 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** add sp, sp, #?288
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -83,7 +91,7 @@ test_2 (void) ...@@ -83,7 +91,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_2048.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** mov x12, #?4352 ** mov x12, #?4608
** sub sp, sp, x12 ** sub sp, sp, x12
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
...@@ -16,39 +16,43 @@ ...@@ -16,39 +16,43 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -57,6 +61,10 @@ ...@@ -57,6 +61,10 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** add sp, sp, x12 ** add sp, sp, x12
** ret ** ret
*/ */
...@@ -84,7 +92,7 @@ test_2 (void) ...@@ -84,7 +92,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -122,11 +130,11 @@ test_3 (void) ...@@ -122,11 +130,11 @@ test_3 (void)
/* /*
** test_4: ** test_4:
** sub sp, sp, #256 ** sub sp, sp, #32
** str p4, \[sp\] ** str p4, \[sp\]
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** add sp, sp, #?256 ** add sp, sp, #?32
** ret ** ret
*/ */
svbool_t svbool_t
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_256.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** sub sp, sp, #544 ** sub sp, sp, #576
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -15,39 +15,43 @@ ...@@ -15,39 +15,43 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -56,7 +60,11 @@ ...@@ -56,7 +60,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** add sp, sp, #?544 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** add sp, sp, #?576
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -83,7 +91,7 @@ test_2 (void) ...@@ -83,7 +91,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -121,11 +129,11 @@ test_3 (void) ...@@ -121,11 +129,11 @@ test_3 (void)
/* /*
** test_4: ** test_4:
** sub sp, sp, #32 ** sub sp, sp, #16
** str p4, \[sp\] ** str p4, \[sp\]
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** add sp, sp, #?32 ** add sp, sp, #?16
** ret ** ret
*/ */
svbool_t svbool_t
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_1_512.c
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/* /*
** test_1: ** test_1:
** sub sp, sp, #1088 ** sub sp, sp, #1152
** str p4, \[sp\] ** str p4, \[sp\]
** str p5, \[sp, #1, mul vl\] ** str p5, \[sp, #1, mul vl\]
** str p6, \[sp, #2, mul vl\] ** str p6, \[sp, #2, mul vl\]
...@@ -15,39 +15,43 @@ ...@@ -15,39 +15,43 @@
** str p9, \[sp, #5, mul vl\] ** str p9, \[sp, #5, mul vl\]
** str p10, \[sp, #6, mul vl\] ** str p10, \[sp, #6, mul vl\]
** str p11, \[sp, #7, mul vl\] ** str p11, \[sp, #7, mul vl\]
** str z8, \[sp, #1, mul vl\] ** str p12, \[sp, #8, mul vl\]
** str z9, \[sp, #2, mul vl\] ** str p13, \[sp, #9, mul vl\]
** str z10, \[sp, #3, mul vl\] ** str p14, \[sp, #10, mul vl\]
** str z11, \[sp, #4, mul vl\] ** str p15, \[sp, #11, mul vl\]
** str z12, \[sp, #5, mul vl\] ** str z8, \[sp, #2, mul vl\]
** str z13, \[sp, #6, mul vl\] ** str z9, \[sp, #3, mul vl\]
** str z14, \[sp, #7, mul vl\] ** str z10, \[sp, #4, mul vl\]
** str z15, \[sp, #8, mul vl\] ** str z11, \[sp, #5, mul vl\]
** str z16, \[sp, #9, mul vl\] ** str z12, \[sp, #6, mul vl\]
** str z17, \[sp, #10, mul vl\] ** str z13, \[sp, #7, mul vl\]
** str z18, \[sp, #11, mul vl\] ** str z14, \[sp, #8, mul vl\]
** str z19, \[sp, #12, mul vl\] ** str z15, \[sp, #9, mul vl\]
** str z20, \[sp, #13, mul vl\] ** str z16, \[sp, #10, mul vl\]
** str z21, \[sp, #14, mul vl\] ** str z17, \[sp, #11, mul vl\]
** str z22, \[sp, #15, mul vl\] ** str z18, \[sp, #12, mul vl\]
** str z23, \[sp, #16, mul vl\] ** str z19, \[sp, #13, mul vl\]
** str z20, \[sp, #14, mul vl\]
** str z21, \[sp, #15, mul vl\]
** str z22, \[sp, #16, mul vl\]
** str z23, \[sp, #17, mul vl\]
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** ldr z8, \[sp, #1, mul vl\] ** ldr z8, \[sp, #2, mul vl\]
** ldr z9, \[sp, #2, mul vl\] ** ldr z9, \[sp, #3, mul vl\]
** ldr z10, \[sp, #3, mul vl\] ** ldr z10, \[sp, #4, mul vl\]
** ldr z11, \[sp, #4, mul vl\] ** ldr z11, \[sp, #5, mul vl\]
** ldr z12, \[sp, #5, mul vl\] ** ldr z12, \[sp, #6, mul vl\]
** ldr z13, \[sp, #6, mul vl\] ** ldr z13, \[sp, #7, mul vl\]
** ldr z14, \[sp, #7, mul vl\] ** ldr z14, \[sp, #8, mul vl\]
** ldr z15, \[sp, #8, mul vl\] ** ldr z15, \[sp, #9, mul vl\]
** ldr z16, \[sp, #9, mul vl\] ** ldr z16, \[sp, #10, mul vl\]
** ldr z17, \[sp, #10, mul vl\] ** ldr z17, \[sp, #11, mul vl\]
** ldr z18, \[sp, #11, mul vl\] ** ldr z18, \[sp, #12, mul vl\]
** ldr z19, \[sp, #12, mul vl\] ** ldr z19, \[sp, #13, mul vl\]
** ldr z20, \[sp, #13, mul vl\] ** ldr z20, \[sp, #14, mul vl\]
** ldr z21, \[sp, #14, mul vl\] ** ldr z21, \[sp, #15, mul vl\]
** ldr z22, \[sp, #15, mul vl\] ** ldr z22, \[sp, #16, mul vl\]
** ldr z23, \[sp, #16, mul vl\] ** ldr z23, \[sp, #17, mul vl\]
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** ldr p5, \[sp, #1, mul vl\] ** ldr p5, \[sp, #1, mul vl\]
** ldr p6, \[sp, #2, mul vl\] ** ldr p6, \[sp, #2, mul vl\]
...@@ -56,7 +60,11 @@ ...@@ -56,7 +60,11 @@
** ldr p9, \[sp, #5, mul vl\] ** ldr p9, \[sp, #5, mul vl\]
** ldr p10, \[sp, #6, mul vl\] ** ldr p10, \[sp, #6, mul vl\]
** ldr p11, \[sp, #7, mul vl\] ** ldr p11, \[sp, #7, mul vl\]
** add sp, sp, #?1088 ** ldr p12, \[sp, #8, mul vl\]
** ldr p13, \[sp, #9, mul vl\]
** ldr p14, \[sp, #10, mul vl\]
** ldr p15, \[sp, #11, mul vl\]
** add sp, sp, #?1152
** ret ** ret
*/ */
svbool_t svbool_t
...@@ -83,7 +91,7 @@ test_2 (void) ...@@ -83,7 +91,7 @@ test_2 (void)
asm volatile ("" ::: asm volatile ("" :::
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7",
"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
"p0", "p1", "p2", "p3", "p12", "p13", "p14", "p15"); "p0", "p1", "p2", "p3");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -121,11 +129,11 @@ test_3 (void) ...@@ -121,11 +129,11 @@ test_3 (void)
/* /*
** test_4: ** test_4:
** sub sp, sp, #64 ** sub sp, sp, #16
** str p4, \[sp\] ** str p4, \[sp\]
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** ldr p4, \[sp\] ** ldr p4, \[sp\]
** add sp, sp, #?64 ** add sp, sp, #?16
** ret ** ret
*/ */
svbool_t svbool_t
......
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_1024.c
...@@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, ...@@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int,
/* /*
** test_1: ** test_1:
** sub sp, sp, #144 ** sub sp, sp, #144
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?144 ** add sp, sp, #?144
** ret ** ret
*/ */
...@@ -21,7 +21,7 @@ svbool_t ...@@ -21,7 +21,7 @@ svbool_t
test_1 (void) test_1 (void)
{ {
volatile int x = 1; volatile int x = 1;
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -30,10 +30,10 @@ test_1 (void) ...@@ -30,10 +30,10 @@ test_1 (void)
** sub sp, sp, #176 ** sub sp, sp, #176
** stp x24, x25, \[sp, 128\] ** stp x24, x25, \[sp, 128\]
** str x26, \[sp, 144\] ** str x26, \[sp, 144\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 128\] ** ldp x24, x25, \[sp, 128\]
** ldr x26, \[sp, 144\] ** ldr x26, \[sp, 144\]
** add sp, sp, #?176 ** add sp, sp, #?176
...@@ -43,7 +43,7 @@ svbool_t ...@@ -43,7 +43,7 @@ svbool_t
test_2 (void) test_2 (void)
{ {
volatile int x = 1; volatile int x = 1;
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -53,10 +53,10 @@ test_2 (void) ...@@ -53,10 +53,10 @@ test_2 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x24, x25, \[sp, 128\] ** stp x24, x25, \[sp, 128\]
** str x26, \[sp, 144\] ** str x26, \[sp, 144\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 128\] ** ldp x24, x25, \[sp, 128\]
** ldr x26, \[sp, 144\] ** ldr x26, \[sp, 144\]
** add sp, sp, x12 ** add sp, sp, x12
...@@ -66,17 +66,17 @@ svbool_t ...@@ -66,17 +66,17 @@ svbool_t
test_3 (void) test_3 (void)
{ {
volatile int x[1024]; volatile int x[1024];
asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
/* /*
** test_4: ** test_4:
** sub sp, sp, #256 ** sub sp, sp, #256
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.h, vl64 ** ptrue p0\.h, vl64
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?256 ** add sp, sp, #?256
** ret ** ret
*/ */
...@@ -85,7 +85,7 @@ test_4 (void) ...@@ -85,7 +85,7 @@ test_4 (void)
{ {
volatile svint32_t b; volatile svint32_t b;
b = svdup_s32 (1); b = svdup_s32 (1);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b16 (); return svptrue_b16 ();
} }
...@@ -94,10 +94,10 @@ test_4 (void) ...@@ -94,10 +94,10 @@ test_4 (void)
** sub sp, sp, #288 ** sub sp, sp, #288
** stp x24, x25, \[sp, 128\] ** stp x24, x25, \[sp, 128\]
** str x26, \[sp, 144\] ** str x26, \[sp, 144\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.h, vl64 ** ptrue p0\.h, vl64
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 128\] ** ldp x24, x25, \[sp, 128\]
** ldr x26, \[sp, 144\] ** ldr x26, \[sp, 144\]
** add sp, sp, #?288 ** add sp, sp, #?288
...@@ -108,7 +108,7 @@ test_5 (void) ...@@ -108,7 +108,7 @@ test_5 (void)
{ {
volatile svint32_t b; volatile svint32_t b;
b = svdup_s32 (1); b = svdup_s32 (1);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b16 (); return svptrue_b16 ();
} }
...@@ -117,11 +117,11 @@ test_5 (void) ...@@ -117,11 +117,11 @@ test_5 (void)
** stp x29, x30, \[sp, -16\]! ** stp x29, x30, \[sp, -16\]!
** mov x29, sp ** mov x29, sp
** sub sp, sp, #128 ** sub sp, sp, #128
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?128 ** add sp, sp, #?128
** ldp x29, x30, \[sp\], 16 ** ldp x29, x30, \[sp\], 16
** ret ** ret
...@@ -130,7 +130,7 @@ svbool_t ...@@ -130,7 +130,7 @@ svbool_t
test_6 (void) test_6 (void)
{ {
take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -140,12 +140,12 @@ test_6 (void) ...@@ -140,12 +140,12 @@ test_6 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x29, x30, \[sp, 128\] ** stp x29, x30, \[sp, 128\]
** add x29, sp, #?128 ** add x29, sp, #?128
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?128 ** add sp, sp, #?128
** ldp x29, x30, \[sp\] ** ldp x29, x30, \[sp\]
** mov x12, #?4112 ** mov x12, #?4112
...@@ -157,7 +157,7 @@ test_7 (void) ...@@ -157,7 +157,7 @@ test_7 (void)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -169,12 +169,12 @@ test_7 (void) ...@@ -169,12 +169,12 @@ test_7 (void)
** add x29, sp, #?128 ** add x29, sp, #?128
** stp x24, x25, \[sp, 144\] ** stp x24, x25, \[sp, 144\]
** str x26, \[sp, 160\] ** str x26, \[sp, 160\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?128 ** add sp, sp, #?128
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -188,7 +188,7 @@ test_8 (void) ...@@ -188,7 +188,7 @@ test_8 (void)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -198,12 +198,12 @@ test_8 (void) ...@@ -198,12 +198,12 @@ test_8 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x29, x30, \[sp, 128\] ** stp x29, x30, \[sp, 128\]
** add x29, sp, #?128 ** add x29, sp, #?128
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** sub sp, x29, #128 ** sub sp, x29, #128
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?128 ** add sp, sp, #?128
** ldp x29, x30, \[sp\] ** ldp x29, x30, \[sp\]
** mov x12, #?4112 ** mov x12, #?4112
...@@ -215,7 +215,7 @@ test_9 (int n) ...@@ -215,7 +215,7 @@ test_9 (int n)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -227,12 +227,12 @@ test_9 (int n) ...@@ -227,12 +227,12 @@ test_9 (int n)
** add x29, sp, #?128 ** add x29, sp, #?128
** stp x24, x25, \[sp, 144\] ** stp x24, x25, \[sp, 144\]
** str x26, \[sp, 160\] ** str x26, \[sp, 160\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** sub sp, x29, #128 ** sub sp, x29, #128
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?128 ** add sp, sp, #?128
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -246,7 +246,7 @@ test_10 (int n) ...@@ -246,7 +246,7 @@ test_10 (int n)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -261,12 +261,12 @@ test_10 (int n) ...@@ -261,12 +261,12 @@ test_10 (int n)
** add x29, sp, #?128 ** add x29, sp, #?128
** stp x24, x25, \[sp, 144\] ** stp x24, x25, \[sp, 144\]
** str x26, \[sp, 160\] ** str x26, \[sp, 160\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl128 ** ptrue p0\.b, vl128
** sub sp, x29, #128 ** sub sp, x29, #128
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?128 ** add sp, sp, #?128
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -280,6 +280,6 @@ test_11 (int n) ...@@ -280,6 +280,6 @@ test_11 (int n)
{ {
volatile int x[0x7ee4]; volatile int x[0x7ee4];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_2048.c
...@@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, ...@@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int,
/* /*
** test_1: ** test_1:
** sub sp, sp, #272 ** sub sp, sp, #272
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?272 ** add sp, sp, #?272
** ret ** ret
*/ */
...@@ -21,7 +21,7 @@ svbool_t ...@@ -21,7 +21,7 @@ svbool_t
test_1 (void) test_1 (void)
{ {
volatile int x = 1; volatile int x = 1;
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -30,10 +30,10 @@ test_1 (void) ...@@ -30,10 +30,10 @@ test_1 (void)
** sub sp, sp, #304 ** sub sp, sp, #304
** stp x24, x25, \[sp, 256\] ** stp x24, x25, \[sp, 256\]
** str x26, \[sp, 272\] ** str x26, \[sp, 272\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 256\] ** ldp x24, x25, \[sp, 256\]
** ldr x26, \[sp, 272\] ** ldr x26, \[sp, 272\]
** add sp, sp, #?304 ** add sp, sp, #?304
...@@ -43,7 +43,7 @@ svbool_t ...@@ -43,7 +43,7 @@ svbool_t
test_2 (void) test_2 (void)
{ {
volatile int x = 1; volatile int x = 1;
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -53,10 +53,10 @@ test_2 (void) ...@@ -53,10 +53,10 @@ test_2 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x24, x25, \[sp, 256\] ** stp x24, x25, \[sp, 256\]
** str x26, \[sp, 272\] ** str x26, \[sp, 272\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 256\] ** ldp x24, x25, \[sp, 256\]
** ldr x26, \[sp, 272\] ** ldr x26, \[sp, 272\]
** add sp, sp, x12 ** add sp, sp, x12
...@@ -66,17 +66,17 @@ svbool_t ...@@ -66,17 +66,17 @@ svbool_t
test_3 (void) test_3 (void)
{ {
volatile int x[1024]; volatile int x[1024];
asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
/* /*
** test_4: ** test_4:
** sub sp, sp, #512 ** sub sp, sp, #512
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.h, vl128 ** ptrue p0\.h, vl128
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?512 ** add sp, sp, #?512
** ret ** ret
*/ */
...@@ -85,7 +85,7 @@ test_4 (void) ...@@ -85,7 +85,7 @@ test_4 (void)
{ {
volatile svint32_t b; volatile svint32_t b;
b = svdup_s32 (1); b = svdup_s32 (1);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b16 (); return svptrue_b16 ();
} }
...@@ -94,10 +94,10 @@ test_4 (void) ...@@ -94,10 +94,10 @@ test_4 (void)
** sub sp, sp, #544 ** sub sp, sp, #544
** stp x24, x25, \[sp, 256\] ** stp x24, x25, \[sp, 256\]
** str x26, \[sp, 272\] ** str x26, \[sp, 272\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.h, vl128 ** ptrue p0\.h, vl128
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 256\] ** ldp x24, x25, \[sp, 256\]
** ldr x26, \[sp, 272\] ** ldr x26, \[sp, 272\]
** add sp, sp, #?544 ** add sp, sp, #?544
...@@ -108,7 +108,7 @@ test_5 (void) ...@@ -108,7 +108,7 @@ test_5 (void)
{ {
volatile svint32_t b; volatile svint32_t b;
b = svdup_s32 (1); b = svdup_s32 (1);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b16 (); return svptrue_b16 ();
} }
...@@ -117,11 +117,11 @@ test_5 (void) ...@@ -117,11 +117,11 @@ test_5 (void)
** stp x29, x30, \[sp, -16\]! ** stp x29, x30, \[sp, -16\]!
** mov x29, sp ** mov x29, sp
** sub sp, sp, #256 ** sub sp, sp, #256
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?256 ** add sp, sp, #?256
** ldp x29, x30, \[sp\], 16 ** ldp x29, x30, \[sp\], 16
** ret ** ret
...@@ -130,7 +130,7 @@ svbool_t ...@@ -130,7 +130,7 @@ svbool_t
test_6 (void) test_6 (void)
{ {
take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -140,12 +140,12 @@ test_6 (void) ...@@ -140,12 +140,12 @@ test_6 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x29, x30, \[sp, 256\] ** stp x29, x30, \[sp, 256\]
** add x29, sp, #?256 ** add x29, sp, #?256
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?256 ** add sp, sp, #?256
** ldp x29, x30, \[sp\] ** ldp x29, x30, \[sp\]
** mov x12, #?4112 ** mov x12, #?4112
...@@ -157,7 +157,7 @@ test_7 (void) ...@@ -157,7 +157,7 @@ test_7 (void)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -169,12 +169,12 @@ test_7 (void) ...@@ -169,12 +169,12 @@ test_7 (void)
** add x29, sp, #?256 ** add x29, sp, #?256
** stp x24, x25, \[sp, 272\] ** stp x24, x25, \[sp, 272\]
** str x26, \[sp, 288\] ** str x26, \[sp, 288\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?256 ** add sp, sp, #?256
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -188,7 +188,7 @@ test_8 (void) ...@@ -188,7 +188,7 @@ test_8 (void)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -198,12 +198,12 @@ test_8 (void) ...@@ -198,12 +198,12 @@ test_8 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x29, x30, \[sp, 256\] ** stp x29, x30, \[sp, 256\]
** add x29, sp, #?256 ** add x29, sp, #?256
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** sub sp, x29, #256 ** sub sp, x29, #256
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?256 ** add sp, sp, #?256
** ldp x29, x30, \[sp\] ** ldp x29, x30, \[sp\]
** mov x12, #?4112 ** mov x12, #?4112
...@@ -215,7 +215,7 @@ test_9 (int n) ...@@ -215,7 +215,7 @@ test_9 (int n)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -227,12 +227,12 @@ test_9 (int n) ...@@ -227,12 +227,12 @@ test_9 (int n)
** add x29, sp, #?256 ** add x29, sp, #?256
** stp x24, x25, \[sp, 272\] ** stp x24, x25, \[sp, 272\]
** str x26, \[sp, 288\] ** str x26, \[sp, 288\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** sub sp, x29, #256 ** sub sp, x29, #256
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?256 ** add sp, sp, #?256
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -246,7 +246,7 @@ test_10 (int n) ...@@ -246,7 +246,7 @@ test_10 (int n)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -261,12 +261,12 @@ test_10 (int n) ...@@ -261,12 +261,12 @@ test_10 (int n)
** add x29, sp, #?256 ** add x29, sp, #?256
** stp x24, x25, \[sp, 272\] ** stp x24, x25, \[sp, 272\]
** str x26, \[sp, 288\] ** str x26, \[sp, 288\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl256 ** ptrue p0\.b, vl256
** sub sp, x29, #256 ** sub sp, x29, #256
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?256 ** add sp, sp, #?256
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -280,6 +280,6 @@ test_11 (int n) ...@@ -280,6 +280,6 @@ test_11 (int n)
{ {
volatile int x[0x7ee4]; volatile int x[0x7ee4];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_256.c
...@@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, ...@@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int,
/* /*
** test_1: ** test_1:
** sub sp, sp, #48 ** sub sp, sp, #48
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?48 ** add sp, sp, #?48
** ret ** ret
*/ */
...@@ -21,7 +21,7 @@ svbool_t ...@@ -21,7 +21,7 @@ svbool_t
test_1 (void) test_1 (void)
{ {
volatile int x = 1; volatile int x = 1;
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -30,10 +30,10 @@ test_1 (void) ...@@ -30,10 +30,10 @@ test_1 (void)
** sub sp, sp, #80 ** sub sp, sp, #80
** stp x24, x25, \[sp, 32\] ** stp x24, x25, \[sp, 32\]
** str x26, \[sp, 48\] ** str x26, \[sp, 48\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 32\] ** ldp x24, x25, \[sp, 32\]
** ldr x26, \[sp, 48\] ** ldr x26, \[sp, 48\]
** add sp, sp, #?80 ** add sp, sp, #?80
...@@ -43,7 +43,7 @@ svbool_t ...@@ -43,7 +43,7 @@ svbool_t
test_2 (void) test_2 (void)
{ {
volatile int x = 1; volatile int x = 1;
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -53,10 +53,10 @@ test_2 (void) ...@@ -53,10 +53,10 @@ test_2 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x24, x25, \[sp, 32\] ** stp x24, x25, \[sp, 32\]
** str x26, \[sp, 48\] ** str x26, \[sp, 48\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 32\] ** ldp x24, x25, \[sp, 32\]
** ldr x26, \[sp, 48\] ** ldr x26, \[sp, 48\]
** add sp, sp, x12 ** add sp, sp, x12
...@@ -66,17 +66,17 @@ svbool_t ...@@ -66,17 +66,17 @@ svbool_t
test_3 (void) test_3 (void)
{ {
volatile int x[1024]; volatile int x[1024];
asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
/* /*
** test_4: ** test_4:
** sub sp, sp, #64 ** sub sp, sp, #64
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.h, vl16 ** ptrue p0\.h, vl16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?64 ** add sp, sp, #?64
** ret ** ret
*/ */
...@@ -85,7 +85,7 @@ test_4 (void) ...@@ -85,7 +85,7 @@ test_4 (void)
{ {
volatile svint32_t b; volatile svint32_t b;
b = svdup_s32 (1); b = svdup_s32 (1);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b16 (); return svptrue_b16 ();
} }
...@@ -94,10 +94,10 @@ test_4 (void) ...@@ -94,10 +94,10 @@ test_4 (void)
** sub sp, sp, #96 ** sub sp, sp, #96
** stp x24, x25, \[sp, 32\] ** stp x24, x25, \[sp, 32\]
** str x26, \[sp, 48\] ** str x26, \[sp, 48\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.h, vl16 ** ptrue p0\.h, vl16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 32\] ** ldp x24, x25, \[sp, 32\]
** ldr x26, \[sp, 48\] ** ldr x26, \[sp, 48\]
** add sp, sp, #?96 ** add sp, sp, #?96
...@@ -108,7 +108,7 @@ test_5 (void) ...@@ -108,7 +108,7 @@ test_5 (void)
{ {
volatile svint32_t b; volatile svint32_t b;
b = svdup_s32 (1); b = svdup_s32 (1);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b16 (); return svptrue_b16 ();
} }
...@@ -117,11 +117,11 @@ test_5 (void) ...@@ -117,11 +117,11 @@ test_5 (void)
** stp x29, x30, \[sp, -16\]! ** stp x29, x30, \[sp, -16\]!
** mov x29, sp ** mov x29, sp
** sub sp, sp, #32 ** sub sp, sp, #32
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?32 ** add sp, sp, #?32
** ldp x29, x30, \[sp\], 16 ** ldp x29, x30, \[sp\], 16
** ret ** ret
...@@ -130,7 +130,7 @@ svbool_t ...@@ -130,7 +130,7 @@ svbool_t
test_6 (void) test_6 (void)
{ {
take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -140,12 +140,12 @@ test_6 (void) ...@@ -140,12 +140,12 @@ test_6 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x29, x30, \[sp, 32\] ** stp x29, x30, \[sp, 32\]
** add x29, sp, #?32 ** add x29, sp, #?32
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?32 ** add sp, sp, #?32
** ldp x29, x30, \[sp\] ** ldp x29, x30, \[sp\]
** mov x12, #?4112 ** mov x12, #?4112
...@@ -157,7 +157,7 @@ test_7 (void) ...@@ -157,7 +157,7 @@ test_7 (void)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -169,12 +169,12 @@ test_7 (void) ...@@ -169,12 +169,12 @@ test_7 (void)
** add x29, sp, #?32 ** add x29, sp, #?32
** stp x24, x25, \[sp, 48\] ** stp x24, x25, \[sp, 48\]
** str x26, \[sp, 64\] ** str x26, \[sp, 64\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?32 ** add sp, sp, #?32
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -188,7 +188,7 @@ test_8 (void) ...@@ -188,7 +188,7 @@ test_8 (void)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -198,12 +198,12 @@ test_8 (void) ...@@ -198,12 +198,12 @@ test_8 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x29, x30, \[sp, 32\] ** stp x29, x30, \[sp, 32\]
** add x29, sp, #?32 ** add x29, sp, #?32
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** sub sp, x29, #32 ** sub sp, x29, #32
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?32 ** add sp, sp, #?32
** ldp x29, x30, \[sp\] ** ldp x29, x30, \[sp\]
** mov x12, #?4112 ** mov x12, #?4112
...@@ -215,7 +215,7 @@ test_9 (int n) ...@@ -215,7 +215,7 @@ test_9 (int n)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -227,12 +227,12 @@ test_9 (int n) ...@@ -227,12 +227,12 @@ test_9 (int n)
** add x29, sp, #?32 ** add x29, sp, #?32
** stp x24, x25, \[sp, 48\] ** stp x24, x25, \[sp, 48\]
** str x26, \[sp, 64\] ** str x26, \[sp, 64\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** sub sp, x29, #32 ** sub sp, x29, #32
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?32 ** add sp, sp, #?32
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -246,7 +246,7 @@ test_10 (int n) ...@@ -246,7 +246,7 @@ test_10 (int n)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -260,12 +260,12 @@ test_10 (int n) ...@@ -260,12 +260,12 @@ test_10 (int n)
** add x29, sp, #?32 ** add x29, sp, #?32
** stp x24, x25, \[sp, 48\] ** stp x24, x25, \[sp, 48\]
** str x26, \[sp, 64\] ** str x26, \[sp, 64\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl32 ** ptrue p0\.b, vl32
** sub sp, x29, #32 ** sub sp, x29, #32
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?32 ** add sp, sp, #?32
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -279,6 +279,6 @@ test_11 (int n) ...@@ -279,6 +279,6 @@ test_11 (int n)
{ {
volatile int x[0x7ee4]; volatile int x[0x7ee4];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
gcc/testsuite/gcc.target/aarch64/sve/pcs/stack_clash_2_512.c
...@@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int, ...@@ -10,10 +10,10 @@ svbool_t take_stack_args (volatile void *, void *, int, int, int,
/* /*
** test_1: ** test_1:
** sub sp, sp, #80 ** sub sp, sp, #80
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?80 ** add sp, sp, #?80
** ret ** ret
*/ */
...@@ -21,7 +21,7 @@ svbool_t ...@@ -21,7 +21,7 @@ svbool_t
test_1 (void) test_1 (void)
{ {
volatile int x = 1; volatile int x = 1;
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -30,10 +30,10 @@ test_1 (void) ...@@ -30,10 +30,10 @@ test_1 (void)
** sub sp, sp, #112 ** sub sp, sp, #112
** stp x24, x25, \[sp, 64\] ** stp x24, x25, \[sp, 64\]
** str x26, \[sp, 80\] ** str x26, \[sp, 80\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 64\] ** ldp x24, x25, \[sp, 64\]
** ldr x26, \[sp, 80\] ** ldr x26, \[sp, 80\]
** add sp, sp, #?112 ** add sp, sp, #?112
...@@ -43,7 +43,7 @@ svbool_t ...@@ -43,7 +43,7 @@ svbool_t
test_2 (void) test_2 (void)
{ {
volatile int x = 1; volatile int x = 1;
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -53,10 +53,10 @@ test_2 (void) ...@@ -53,10 +53,10 @@ test_2 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x24, x25, \[sp, 64\] ** stp x24, x25, \[sp, 64\]
** str x26, \[sp, 80\] ** str x26, \[sp, 80\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 64\] ** ldp x24, x25, \[sp, 64\]
** ldr x26, \[sp, 80\] ** ldr x26, \[sp, 80\]
** add sp, sp, x12 ** add sp, sp, x12
...@@ -66,17 +66,17 @@ svbool_t ...@@ -66,17 +66,17 @@ svbool_t
test_3 (void) test_3 (void)
{ {
volatile int x[1024]; volatile int x[1024];
asm volatile ("" :: "r" (x) : "p4", "x24", "x25", "x26"); asm volatile ("" :: "r" (x) : "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
/* /*
** test_4: ** test_4:
** sub sp, sp, #128 ** sub sp, sp, #128
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.h, vl32 ** ptrue p0\.h, vl32
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?128 ** add sp, sp, #?128
** ret ** ret
*/ */
...@@ -85,7 +85,7 @@ test_4 (void) ...@@ -85,7 +85,7 @@ test_4 (void)
{ {
volatile svint32_t b; volatile svint32_t b;
b = svdup_s32 (1); b = svdup_s32 (1);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b16 (); return svptrue_b16 ();
} }
...@@ -94,10 +94,10 @@ test_4 (void) ...@@ -94,10 +94,10 @@ test_4 (void)
** sub sp, sp, #160 ** sub sp, sp, #160
** stp x24, x25, \[sp, 64\] ** stp x24, x25, \[sp, 64\]
** str x26, \[sp, 80\] ** str x26, \[sp, 80\]
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.h, vl32 ** ptrue p0\.h, vl32
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** ldp x24, x25, \[sp, 64\] ** ldp x24, x25, \[sp, 64\]
** ldr x26, \[sp, 80\] ** ldr x26, \[sp, 80\]
** add sp, sp, #?160 ** add sp, sp, #?160
...@@ -108,7 +108,7 @@ test_5 (void) ...@@ -108,7 +108,7 @@ test_5 (void)
{ {
volatile svint32_t b; volatile svint32_t b;
b = svdup_s32 (1); b = svdup_s32 (1);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b16 (); return svptrue_b16 ();
} }
...@@ -117,11 +117,11 @@ test_5 (void) ...@@ -117,11 +117,11 @@ test_5 (void)
** stp x29, x30, \[sp, -16\]! ** stp x29, x30, \[sp, -16\]!
** mov x29, sp ** mov x29, sp
** sub sp, sp, #64 ** sub sp, sp, #64
** str p4, \[sp\] ** str z16, \[sp\]
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?64 ** add sp, sp, #?64
** ldp x29, x30, \[sp\], 16 ** ldp x29, x30, \[sp\], 16
** ret ** ret
...@@ -130,7 +130,7 @@ svbool_t ...@@ -130,7 +130,7 @@ svbool_t
test_6 (void) test_6 (void)
{ {
take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (0, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -140,12 +140,12 @@ test_6 (void) ...@@ -140,12 +140,12 @@ test_6 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x29, x30, \[sp, 64\] ** stp x29, x30, \[sp, 64\]
** add x29, sp, #?64 ** add x29, sp, #?64
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?64 ** add sp, sp, #?64
** ldp x29, x30, \[sp\] ** ldp x29, x30, \[sp\]
** mov x12, #?4112 ** mov x12, #?4112
...@@ -157,7 +157,7 @@ test_7 (void) ...@@ -157,7 +157,7 @@ test_7 (void)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -169,12 +169,12 @@ test_7 (void) ...@@ -169,12 +169,12 @@ test_7 (void)
** add x29, sp, #?64 ** add x29, sp, #?64
** stp x24, x25, \[sp, 80\] ** stp x24, x25, \[sp, 80\]
** str x26, \[sp, 96\] ** str x26, \[sp, 96\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** add sp, sp, #?16 ** add sp, sp, #?16
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?64 ** add sp, sp, #?64
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -188,7 +188,7 @@ test_8 (void) ...@@ -188,7 +188,7 @@ test_8 (void)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, 0, 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -198,12 +198,12 @@ test_8 (void) ...@@ -198,12 +198,12 @@ test_8 (void)
** sub sp, sp, x12 ** sub sp, sp, x12
** stp x29, x30, \[sp, 64\] ** stp x29, x30, \[sp, 64\]
** add x29, sp, #?64 ** add x29, sp, #?64
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** sub sp, x29, #64 ** sub sp, x29, #64
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?64 ** add sp, sp, #?64
** ldp x29, x30, \[sp\] ** ldp x29, x30, \[sp\]
** mov x12, #?4112 ** mov x12, #?4112
...@@ -215,7 +215,7 @@ test_9 (int n) ...@@ -215,7 +215,7 @@ test_9 (int n)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4"); asm volatile ("" ::: "z16");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -227,12 +227,12 @@ test_9 (int n) ...@@ -227,12 +227,12 @@ test_9 (int n)
** add x29, sp, #?64 ** add x29, sp, #?64
** stp x24, x25, \[sp, 80\] ** stp x24, x25, \[sp, 80\]
** str x26, \[sp, 96\] ** str x26, \[sp, 96\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** sub sp, x29, #64 ** sub sp, x29, #64
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?64 ** add sp, sp, #?64
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -246,7 +246,7 @@ test_10 (int n) ...@@ -246,7 +246,7 @@ test_10 (int n)
{ {
volatile int x[1024]; volatile int x[1024];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
...@@ -261,12 +261,12 @@ test_10 (int n) ...@@ -261,12 +261,12 @@ test_10 (int n)
** add x29, sp, #?64 ** add x29, sp, #?64
** stp x24, x25, \[sp, 80\] ** stp x24, x25, \[sp, 80\]
** str x26, \[sp, 96\] ** str x26, \[sp, 96\]
** str p4, \[sp\] ** str z16, \[sp\]
** sub sp, sp, #16 ** sub sp, sp, #16
** ... ** ...
** ptrue p0\.b, vl64 ** ptrue p0\.b, vl64
** sub sp, x29, #64 ** sub sp, x29, #64
** ldr p4, \[sp\] ** ldr z16, \[sp\]
** add sp, sp, #?64 ** add sp, sp, #?64
** ldp x24, x25, \[sp, 16\] ** ldp x24, x25, \[sp, 16\]
** ldr x26, \[sp, 32\] ** ldr x26, \[sp, 32\]
...@@ -280,6 +280,6 @@ test_11 (int n) ...@@ -280,6 +280,6 @@ test_11 (int n)
{ {
volatile int x[0x7ee4]; volatile int x[0x7ee4];
take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7); take_stack_args (x, __builtin_alloca (n), 1, 2, 3, 4, 5, 6, 7);
asm volatile ("" ::: "p4", "x24", "x25", "x26"); asm volatile ("" ::: "z16", "x24", "x25", "x26");
return svptrue_b8 (); return svptrue_b8 ();
} }
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