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riscv-gcc-1
Commit 0dad5b33 by Srinath Parvathaneni Committed by Kyrylo Tkachov
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[ARM][GCC][1/3x]: MVE intrinsics with ternary operands. 

This patch supports following MVE ACLE intrinsics with ternary operands.

vabavq_s8, vabavq_s16, vabavq_s32, vbicq_m_n_s16, vbicq_m_n_s32, vbicq_m_n_u16, vbicq_m_n_u32, vcmpeqq_m_f16, vcmpeqq_m_f32, vcvtaq_m_s16_f16, vcvtaq_m_u16_f16, vcvtaq_m_s32_f32, vcvtaq_m_u32_f32, vcvtq_m_f16_s16, vcvtq_m_f16_u16, vcvtq_m_f32_s32, vcvtq_m_f32_u32, vqrshrnbq_n_s16, vqrshrnbq_n_u16, vqrshrnbq_n_s32, vqrshrnbq_n_u32, vqrshrunbq_n_s16, vqrshrunbq_n_s32, vrmlaldavhaq_s32, vrmlaldavhaq_u32, vshlcq_s8, vshlcq_u8, vshlcq_s16, vshlcq_u16, vshlcq_s32, vshlcq_u32, vabavq_s8, vabavq_s16, vabavq_s32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
	Define qualifier for ternary operands.
	(TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (vabavq_s8): Define macro.
	(vabavq_s16): Likewise.
	(vabavq_s32): Likewise.
	(vbicq_m_n_s16): Likewise.
	(vbicq_m_n_s32): Likewise.
	(vbicq_m_n_u16): Likewise.
	(vbicq_m_n_u32): Likewise.
	(vcmpeqq_m_f16): Likewise.
	(vcmpeqq_m_f32): Likewise.
	(vcvtaq_m_s16_f16): Likewise.
	(vcvtaq_m_u16_f16): Likewise.
	(vcvtaq_m_s32_f32): Likewise.
	(vcvtaq_m_u32_f32): Likewise.
	(vcvtq_m_f16_s16): Likewise.
	(vcvtq_m_f16_u16): Likewise.
	(vcvtq_m_f32_s32): Likewise.
	(vcvtq_m_f32_u32): Likewise.
	(vqrshrnbq_n_s16): Likewise.
	(vqrshrnbq_n_u16): Likewise.
	(vqrshrnbq_n_s32): Likewise.
	(vqrshrnbq_n_u32): Likewise.
	(vqrshrunbq_n_s16): Likewise.
	(vqrshrunbq_n_s32): Likewise.
	(vrmlaldavhaq_s32): Likewise.
	(vrmlaldavhaq_u32): Likewise.
	(vshlcq_s8): Likewise.
	(vshlcq_u8): Likewise.
	(vshlcq_s16): Likewise.
	(vshlcq_u16): Likewise.
	(vshlcq_s32): Likewise.
	(vshlcq_u32): Likewise.
	(vabavq_u8): Likewise.
	(vabavq_u16): Likewise.
	(vabavq_u32): Likewise.
	(__arm_vabavq_s8): Define intrinsic.
	(__arm_vabavq_s16): Likewise.
	(__arm_vabavq_s32): Likewise.
	(__arm_vabavq_u8): Likewise.
	(__arm_vabavq_u16): Likewise.
	(__arm_vabavq_u32): Likewise.
	(__arm_vbicq_m_n_s16): Likewise.
	(__arm_vbicq_m_n_s32): Likewise.
	(__arm_vbicq_m_n_u16): Likewise.
	(__arm_vbicq_m_n_u32): Likewise.
	(__arm_vqrshrnbq_n_s16): Likewise.
	(__arm_vqrshrnbq_n_u16): Likewise.
	(__arm_vqrshrnbq_n_s32): Likewise.
	(__arm_vqrshrnbq_n_u32): Likewise.
	(__arm_vqrshrunbq_n_s16): Likewise.
	(__arm_vqrshrunbq_n_s32): Likewise.
	(__arm_vrmlaldavhaq_s32): Likewise.
	(__arm_vrmlaldavhaq_u32): Likewise.
	(__arm_vshlcq_s8): Likewise.
	(__arm_vshlcq_u8): Likewise.
	(__arm_vshlcq_s16): Likewise.
	(__arm_vshlcq_u16): Likewise.
	(__arm_vshlcq_s32): Likewise.
	(__arm_vshlcq_u32): Likewise.
	(__arm_vcmpeqq_m_f16): Likewise.
	(__arm_vcmpeqq_m_f32): Likewise.
	(__arm_vcvtaq_m_s16_f16): Likewise.
	(__arm_vcvtaq_m_u16_f16): Likewise.
	(__arm_vcvtaq_m_s32_f32): Likewise.
	(__arm_vcvtaq_m_u32_f32): Likewise.
	(__arm_vcvtq_m_f16_s16): Likewise.
	(__arm_vcvtq_m_f16_u16): Likewise.
	(__arm_vcvtq_m_f32_s32): Likewise.
	(__arm_vcvtq_m_f32_u32): Likewise.
	(vcvtaq_m): Define polymorphic variant.
	(vcvtq_m): Likewise.
	(vabavq): Likewise.
	(vshlcq): Likewise.
	(vbicq_m_n): Likewise.
	(vqrshrnbq_n): Likewise.
	(vqrshrunbq_n): Likewise.
	* config/arm/arm_mve_builtins.def
	(TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
	(TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
	(TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
	* config/arm/mve.md (VBICQ_M_N): Define iterator.
	(VCVTAQ_M): Likewise.
	(VCVTQ_M_TO_F): Likewise.
	(VQRSHRNBQ_N): Likewise.
	(VABAVQ): Likewise.
	(VSHLCQ): Likewise.
	(VRMLALDAVHAQ): Likewise.
	(mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
	(mve_vcmpeqq_m_f<mode>): Likewise.
	(mve_vcvtaq_m_<supf><mode>): Likewise.
	(mve_vcvtq_m_to_f_<supf><mode>): Likewise.
	(mve_vqrshrnbq_n_<supf><mode>): Likewise.
	(mve_vqrshrunbq_n_s<mode>): Likewise.
	(mve_vrmlaldavhaq_<supf>v4si): Likewise.
	(mve_vabavq_<supf><mode>): Likewise.
	(mve_vshlcq_<supf><mode>): Likewise.
	(mve_vshlcq_<supf><mode>): Likewise.
	(mve_vshlcq_vec_<supf><mode>): Define RTL expand.
	(mve_vshlcq_carry_<supf><mode>): Likewise.

gcc/testsuite/ChangeLog:

2020-03-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vabavq_s16.c: New test.
	* gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.
parent f9355dee
Showing with 1205 additions and 2 deletions
gcc/ChangeLog
......@@ -2,6 +2,135 @@
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
Define qualifier for ternary operands.
(TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
(TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
(TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
(TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
(TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
* config/arm/arm_mve.h (vabavq_s8): Define macro.
(vabavq_s16): Likewise.
(vabavq_s32): Likewise.
(vbicq_m_n_s16): Likewise.
(vbicq_m_n_s32): Likewise.
(vbicq_m_n_u16): Likewise.
(vbicq_m_n_u32): Likewise.
(vcmpeqq_m_f16): Likewise.
(vcmpeqq_m_f32): Likewise.
(vcvtaq_m_s16_f16): Likewise.
(vcvtaq_m_u16_f16): Likewise.
(vcvtaq_m_s32_f32): Likewise.
(vcvtaq_m_u32_f32): Likewise.
(vcvtq_m_f16_s16): Likewise.
(vcvtq_m_f16_u16): Likewise.
(vcvtq_m_f32_s32): Likewise.
(vcvtq_m_f32_u32): Likewise.
(vqrshrnbq_n_s16): Likewise.
(vqrshrnbq_n_u16): Likewise.
(vqrshrnbq_n_s32): Likewise.
(vqrshrnbq_n_u32): Likewise.
(vqrshrunbq_n_s16): Likewise.
(vqrshrunbq_n_s32): Likewise.
(vrmlaldavhaq_s32): Likewise.
(vrmlaldavhaq_u32): Likewise.
(vshlcq_s8): Likewise.
(vshlcq_u8): Likewise.
(vshlcq_s16): Likewise.
(vshlcq_u16): Likewise.
(vshlcq_s32): Likewise.
(vshlcq_u32): Likewise.
(vabavq_u8): Likewise.
(vabavq_u16): Likewise.
(vabavq_u32): Likewise.
(__arm_vabavq_s8): Define intrinsic.
(__arm_vabavq_s16): Likewise.
(__arm_vabavq_s32): Likewise.
(__arm_vabavq_u8): Likewise.
(__arm_vabavq_u16): Likewise.
(__arm_vabavq_u32): Likewise.
(__arm_vbicq_m_n_s16): Likewise.
(__arm_vbicq_m_n_s32): Likewise.
(__arm_vbicq_m_n_u16): Likewise.
(__arm_vbicq_m_n_u32): Likewise.
(__arm_vqrshrnbq_n_s16): Likewise.
(__arm_vqrshrnbq_n_u16): Likewise.
(__arm_vqrshrnbq_n_s32): Likewise.
(__arm_vqrshrnbq_n_u32): Likewise.
(__arm_vqrshrunbq_n_s16): Likewise.
(__arm_vqrshrunbq_n_s32): Likewise.
(__arm_vrmlaldavhaq_s32): Likewise.
(__arm_vrmlaldavhaq_u32): Likewise.
(__arm_vshlcq_s8): Likewise.
(__arm_vshlcq_u8): Likewise.
(__arm_vshlcq_s16): Likewise.
(__arm_vshlcq_u16): Likewise.
(__arm_vshlcq_s32): Likewise.
(__arm_vshlcq_u32): Likewise.
(__arm_vcmpeqq_m_f16): Likewise.
(__arm_vcmpeqq_m_f32): Likewise.
(__arm_vcvtaq_m_s16_f16): Likewise.
(__arm_vcvtaq_m_u16_f16): Likewise.
(__arm_vcvtaq_m_s32_f32): Likewise.
(__arm_vcvtaq_m_u32_f32): Likewise.
(__arm_vcvtq_m_f16_s16): Likewise.
(__arm_vcvtq_m_f16_u16): Likewise.
(__arm_vcvtq_m_f32_s32): Likewise.
(__arm_vcvtq_m_f32_u32): Likewise.
(vcvtaq_m): Define polymorphic variant.
(vcvtq_m): Likewise.
(vabavq): Likewise.
(vshlcq): Likewise.
(vbicq_m_n): Likewise.
(vqrshrnbq_n): Likewise.
(vqrshrunbq_n): Likewise.
* config/arm/arm_mve_builtins.def
(TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
(TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
(TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
(TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
(TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
(TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
* config/arm/mve.md (VBICQ_M_N): Define iterator.
(VCVTAQ_M): Likewise.
(VCVTQ_M_TO_F): Likewise.
(VQRSHRNBQ_N): Likewise.
(VABAVQ): Likewise.
(VSHLCQ): Likewise.
(VRMLALDAVHAQ): Likewise.
(mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
(mve_vcmpeqq_m_f<mode>): Likewise.
(mve_vcvtaq_m_<supf><mode>): Likewise.
(mve_vcvtq_m_to_f_<supf><mode>): Likewise.
(mve_vqrshrnbq_n_<supf><mode>): Likewise.
(mve_vqrshrunbq_n_s<mode>): Likewise.
(mve_vrmlaldavhaq_<supf>v4si): Likewise.
(mve_vabavq_<supf><mode>): Likewise.
(mve_vshlcq_<supf><mode>): Likewise.
(mve_vshlcq_<supf><mode>): Likewise.
(mve_vshlcq_vec_<supf><mode>): Define RTL expand.
(mve_vshlcq_carry_<supf><mode>): Likewise.
2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vqmovntq_u16): Define macro.
(vqmovnbq_u16): Likewise.
(vmulltq_poly_p8): Likewise.
......
gcc/config/arm/arm-builtins.c
......@@ -433,6 +433,96 @@ arm_binop_unone_unone_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define BINOP_UNONE_UNONE_NONE_QUALIFIERS \
(arm_binop_unone_unone_none_qualifiers)
static enum arm_type_qualifiers
arm_ternop_unone_unone_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
qualifier_immediate };
#define TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS \
(arm_ternop_unone_unone_unone_imm_qualifiers)
static enum arm_type_qualifiers
arm_ternop_unone_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_none, qualifier_none };
#define TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS \
(arm_ternop_unone_unone_none_none_qualifiers)
static enum arm_type_qualifiers
arm_ternop_unone_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_none, qualifier_unsigned,
qualifier_immediate };
#define TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS \
(arm_ternop_unone_none_unone_imm_qualifiers)
static enum arm_type_qualifiers
arm_ternop_none_none_unone_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate };
#define TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS \
(arm_ternop_none_none_unone_imm_qualifiers)
static enum arm_type_qualifiers
arm_ternop_unone_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_none,
qualifier_immediate };
#define TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS \
(arm_ternop_unone_unone_none_imm_qualifiers)
static enum arm_type_qualifiers
arm_ternop_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_none,
qualifier_unsigned };
#define TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS \
(arm_ternop_unone_unone_none_unone_qualifiers)
static enum arm_type_qualifiers
arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
qualifier_unsigned };
#define TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS \
(arm_ternop_unone_unone_imm_unone_qualifiers)
static enum arm_type_qualifiers
arm_ternop_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_none, qualifier_none, qualifier_unsigned };
#define TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS \
(arm_ternop_unone_none_none_unone_qualifiers)
static enum arm_type_qualifiers
arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate };
#define TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS \
(arm_ternop_none_none_none_imm_qualifiers)
static enum arm_type_qualifiers
arm_ternop_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_unsigned };
#define TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS \
(arm_ternop_none_none_none_unone_qualifiers)
static enum arm_type_qualifiers
arm_ternop_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_immediate, qualifier_unsigned };
#define TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS \
(arm_ternop_none_none_imm_unone_qualifiers)
static enum arm_type_qualifiers
arm_ternop_none_none_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_unsigned };
#define TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS \
(arm_ternop_none_none_unone_unone_qualifiers)
static enum arm_type_qualifiers
arm_ternop_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
qualifier_unsigned };
#define TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \
(arm_ternop_unone_unone_unone_unone_qualifiers)
static enum arm_type_qualifiers
arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_none };
#define TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS \
(arm_ternop_none_none_none_none_qualifiers)
/* End of Qualifier for MVE builtins. */
/* void ([T element type] *, T, immediate). */
......
gcc/config/arm/mve.md
......@@ -85,7 +85,11 @@
VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
VMULLBQ_POLY_P])
VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F
VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U
VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S
VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U
VRMLALDAVHAQ_U])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
(V8HF "V8HI") (V4SF "V4SI")])
......@@ -146,7 +150,12 @@
(VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
(VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
(VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
(VRMLALDAVHQ_S "s")])
(VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
(VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
(VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
(VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
(VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
(VSHLCQ_U "u")])
(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
......@@ -241,6 +250,13 @@
(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
(define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
(define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
(define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
(define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
(define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
(define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
......@@ -3057,3 +3073,170 @@
"vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vbicq_m_n_s, vbicq_m_n_u])
;;
(define_insn "mve_vbicq_m_n_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:HI 3 "vpr_register_operand" "Up")]
VBICQ_M_N))
]
"TARGET_HAVE_MVE"
"vpst\;vbict.i%#<V_sz_elem> %q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vcmpeqq_m_f])
;;
(define_insn "mve_vcmpeqq_m_f<mode>"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")
(match_operand:HI 3 "vpr_register_operand" "Up")]
VCMPEQQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vcvtaq_m_u, vcvtaq_m_s])
;;
(define_insn "mve_vcvtaq_m_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
(match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
(match_operand:HI 3 "vpr_register_operand" "Up")]
VCVTAQ_M))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
;;
(define_insn "mve_vcvtq_m_to_f_<supf><mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
(match_operand:HI 3 "vpr_register_operand" "Up")]
VCVTQ_M_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vqrshrnbq_n_u, vqrshrnbq_n_s])
;;
(define_insn "mve_vqrshrnbq_n_<supf><mode>"
[
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_8" "Rb")]
VQRSHRNBQ_N))
]
"TARGET_HAVE_MVE"
"vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3"
[(set_attr "type" "mve_move")
])
;;
;; [vqrshrunbq_n_s])
;;
(define_insn "mve_vqrshrunbq_n_s<mode>"
[
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(match_operand:MVE_5 2 "s_register_operand" "w")
(match_operand:SI 3 "mve_imm_8" "Rb")]
VQRSHRUNBQ_N_S))
]
"TARGET_HAVE_MVE"
"vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
])
;;
;; [vrmlaldavhaq_s vrmlaldavhaq_u])
;;
(define_insn "mve_vrmlaldavhaq_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")]
VRMLALDAVHAQ))
]
"TARGET_HAVE_MVE"
"vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
;;
;; [vabavq_s, vabavq_u])
;;
(define_insn "mve_vabavq_<supf><mode>"
[
(set (match_operand:SI 0 "s_register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")]
VABAVQ))
]
"TARGET_HAVE_MVE"
"vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
[(set_attr "type" "mve_move")
])
;;
;; [vshlcq_u vshlcq_s]
;;
(define_expand "mve_vshlcq_vec_<supf><mode>"
[(match_operand:MVE_2 0 "s_register_operand")
(match_operand:MVE_2 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:SI 3 "mve_imm_32")
(unspec:MVE_2 [(const_int 0)] VSHLCQ)]
"TARGET_HAVE_MVE"
{
rtx ignore_wb = gen_reg_rtx (SImode);
emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1],
operands[2], operands[3]));
DONE;
})
(define_expand "mve_vshlcq_carry_<supf><mode>"
[(match_operand:SI 0 "s_register_operand")
(match_operand:MVE_2 1 "s_register_operand")
(match_operand:SI 2 "s_register_operand")
(match_operand:SI 3 "mve_imm_32")
(unspec:MVE_2 [(const_int 0)] VSHLCQ)]
"TARGET_HAVE_MVE"
{
rtx ignore_vec = gen_reg_rtx (<MODE>mode);
emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1],
operands[2], operands[3]));
DONE;
})
(define_insn "mve_vshlcq_<supf><mode>"
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
(match_operand:SI 3 "s_register_operand" "1")
(match_operand:SI 4 "mve_imm_32" "Rf")]
VSHLCQ))
(set (match_operand:SI 1 "s_register_operand" "=r")
(unspec:SI [(match_dup 2)
(match_dup 3)
(match_dup 4)]
VSHLCQ))]
"TARGET_HAVE_MVE"
"vshlc %q0, %1, %4")
gcc/testsuite/ChangeLog
......@@ -2,6 +2,45 @@
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabavq_s16.c: New test.
* gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.
2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabdq_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
......
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, int16x8_t b, int16x8_t c)
{
return vabavq_s16 (a, b, c);
}
/* { dg-final { scan-assembler "vabav.s16" } } */
uint32_t
foo1 (uint32_t a, int16x8_t b, int16x8_t c)
{
return vabavq (a, b, c);
}
/* { dg-final { scan-assembler "vabav.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, int32x4_t b, int32x4_t c)
{
return vabavq_s32 (a, b, c);
}
/* { dg-final { scan-assembler "vabav.s32" } } */
uint32_t
foo1 (uint32_t a, int32x4_t b, int32x4_t c)
{
return vabavq (a, b, c);
}
/* { dg-final { scan-assembler "vabav.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, int8x16_t b, int8x16_t c)
{
return vabavq_s8 (a, b, c);
}
/* { dg-final { scan-assembler "vabav.s8" } } */
uint32_t
foo1 (uint32_t a, int8x16_t b, int8x16_t c)
{
return vabavq (a, b, c);
}
/* { dg-final { scan-assembler "vabav.s8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, uint16x8_t b, uint16x8_t c)
{
return vabavq_u16 (a, b, c);
}
/* { dg-final { scan-assembler "vabav.u16" } } */
uint32_t
foo1 (uint32_t a, uint16x8_t b, uint16x8_t c)
{
return vabavq (a, b, c);
}
/* { dg-final { scan-assembler "vabav.u16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, uint32x4_t b, uint32x4_t c)
{
return vabavq_u32 (a, b, c);
}
/* { dg-final { scan-assembler "vabav.u32" } } */
uint32_t
foo1 (uint32_t a, uint32x4_t b, uint32x4_t c)
{
return vabavq (a, b, c);
}
/* { dg-final { scan-assembler "vabav.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32_t
foo (uint32_t a, uint8x16_t b, uint8x16_t c)
{
return vabavq_u8 (a, b, c);
}
/* { dg-final { scan-assembler "vabav.u8" } } */
uint32_t
foo1 (uint32_t a, uint8x16_t b, uint8x16_t c)
{
return vabavq (a, b, c);
}
/* { dg-final { scan-assembler "vabav.u8" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a, mve_pred16_t p)
{
return vbicq_m_n_s16 (a, 16, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vbict.i16" } } */
int16x8_t
foo1 (int16x8_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 16, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a, mve_pred16_t p)
{
return vbicq_m_n_s32 (a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vbict.i32" } } */
int32x4_t
foo1 (int32x4_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a, mve_pred16_t p)
{
return vbicq_m_n_u16 (a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vbict.i16" } } */
uint16x8_t
foo1 (uint16x8_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t a, mve_pred16_t p)
{
return vbicq_m_n_u32 (a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vbict.i32" } } */
uint32x4_t
foo1 (uint32x4_t a, mve_pred16_t p)
{
return vbicq_m_n (a, 1, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vcmpeqq_m_f16 (a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcmpt.f16" } } */
mve_pred16_t
foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
{
return vcmpeqq_m (a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
mve_pred16_t
foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vcmpeqq_m_f32 (a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcmpt.f32" } } */
mve_pred16_t
foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
{
return vcmpeqq_m (a, b, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m_s16_f16 (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */
int16x8_t
foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m_s32_f32 (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */
int32x4_t
foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m_u16_f16 (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */
uint16x8_t
foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m_u32_f32 (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */
uint32x4_t
foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
{
return vcvtaq_m (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m_f16_s16 (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
float16x8_t
foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float16x8_t
foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m_f16_u16 (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */
float16x8_t
foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m_f32_s32 (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */
float32x4_t
foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
/* { dg-add-options arm_v8_1m_mve_fp } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
float32x4_t
foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vcvtq_m_f32_u32 (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */
float32x4_t
foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
{
return vcvtq_m (inactive, a, p);
}
/* { dg-final { scan-assembler "vpst" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a, int16x8_t b)
{
return vqrshrnbq_n_s16 (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrnb.s16" } } */
int8x16_t
foo1 (int8x16_t a, int16x8_t b)
{
return vqrshrnbq (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrnb.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a, int32x4_t b)
{
return vqrshrnbq_n_s32 (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrnb.s32" } } */
int16x8_t
foo1 (int16x8_t a, int32x4_t b)
{
return vqrshrnbq (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrnb.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t a, uint16x8_t b)
{
return vqrshrnbq_n_u16 (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrnb.u16" } } */
uint8x16_t
foo1 (uint8x16_t a, uint16x8_t b)
{
return vqrshrnbq (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrnb.u16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a, uint32x4_t b)
{
return vqrshrnbq_n_u32 (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrnb.u32" } } */
uint16x8_t
foo1 (uint16x8_t a, uint32x4_t b)
{
return vqrshrnbq (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrnb.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t a, int16x8_t b)
{
return vqrshrunbq_n_s16 (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrunb.s16" } } */
uint8x16_t
foo1 (uint8x16_t a, int16x8_t b)
{
return vqrshrunbq (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrunb.s16" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a, int32x4_t b)
{
return vqrshrunbq_n_s32 (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrunb.s32" } } */
uint16x8_t
foo1 (uint16x8_t a, int32x4_t b)
{
return vqrshrunbq (a, b, 1);
}
/* { dg-final { scan-assembler "vqrshrunb.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int64_t
foo (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlaldavhaq_s32 (a, b, c);
}
/* { dg-final { scan-assembler "vrmlaldavha.s32" } } */
int64_t
foo1 (int64_t a, int32x4_t b, int32x4_t c)
{
return vrmlaldavhaq (a, b, c);
}
/* { dg-final { scan-assembler "vrmlaldavha.s32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint64_t
foo (uint64_t a, uint32x4_t b, uint32x4_t c)
{
return vrmlaldavhaq_u32 (a, b, c);
}
/* { dg-final { scan-assembler "vrmlaldavha.u32" } } */
uint64_t
foo1 (uint64_t a, uint32x4_t b, uint32x4_t c)
{
return vrmlaldavhaq (a, b, c);
}
/* { dg-final { scan-assembler "vrmlaldavha.u32" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int16x8_t
foo (int16x8_t a, uint32_t * b)
{
return vshlcq_s16 (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
int16x8_t
foo1 (int16x8_t a, uint32_t * b)
{
return vshlcq (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int32x4_t
foo (int32x4_t a, uint32_t * b)
{
return vshlcq_s32 (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
int32x4_t
foo1 (int32x4_t a, uint32_t * b)
{
return vshlcq (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
int8x16_t
foo (int8x16_t a, uint32_t * b)
{
return vshlcq_s8 (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
int8x16_t
foo1 (int8x16_t a, uint32_t * b)
{
return vshlcq (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint16x8_t
foo (uint16x8_t a, uint32_t * b)
{
return vshlcq_u16 (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
uint16x8_t
foo1 (uint16x8_t a, uint32_t * b)
{
return vshlcq (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint32x4_t
foo (uint32x4_t a, uint32_t * b)
{
return vshlcq_u32 (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
uint32x4_t
foo1 (uint32x4_t a, uint32_t * b)
{
return vshlcq (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
#include "arm_mve.h"
uint8x16_t
foo (uint8x16_t a, uint32_t * b)
{
return vshlcq_u8 (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
uint8x16_t
foo1 (uint8x16_t a, uint32_t * b)
{
return vshlcq (a, b, 1);
}
/* { dg-final { scan-assembler "vshlc" } } */
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