The GCN VCC register has 64 CC values in one registers, one bit for each
vector lane.
Previously we avoided problems with invalid optimizations by not declaring
a mode for the comparison operators, but it turns out that causes other
problems (and build warnings).
Instead, the optimization issues can be avoided by setting
STORE_REGISTER_VALUE to -1, meaning that all the bits are significant.
(It would be better if we could set STORE_REGISTER_VALUE according to the
known mask or vector size, but we can't.)
2020-03-18 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
(vec_cmp<mode>di_dup): Likewise.
* config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
