1. 23 Dec, 2019 1 commit
  2. 21 Dec, 2019 1 commit
  3. 16 Dec, 2019 1 commit
  4. 11 Dec, 2019 1 commit
  5. 09 Dec, 2019 1 commit
  6. 28 Nov, 2019 1 commit
  7. 27 Nov, 2019 2 commits
  8. 26 Nov, 2019 1 commit
  9. 24 Nov, 2019 3 commits
  10. 22 Nov, 2019 1 commit
  11. 18 Nov, 2019 1 commit
  12. 15 Nov, 2019 1 commit
  13. 14 Nov, 2019 1 commit
  14. 11 Nov, 2019 1 commit
  15. 06 Nov, 2019 2 commits
  16. 02 Nov, 2019 1 commit
    • [VTA] Performance optimize, remove unnecessary contigious memory use. (#4246) · 008aa838
      * [VTA] Performance optimize, remove unnecessary contigious memory use.
      
      Issue:
      Uop maintain a cache vector to copy uop data into contigious DRAM memory for
      FPGA/Simulator use, but this cache vector not get clear after FPGA/Simulator
      core run, in Resnet18 case, if we printf the cache size in UopQueue::ReadBarrier
      function, we can saw such cache size keep increase, this would cause
      no use data copy and unnecessary contigous DRAM memory malloc.
      
      Analysis:
      This issue caused by not clear cache_ vector when do
      uop_queue_.Reset().
      
      Solution:
      Override BaseQueue Reset function in UopQueue and add cache_ clear
      logic.
      
      * address review comments, remove spacing.
      Hua Jiang committed
  17. 27 Oct, 2019 1 commit
  18. 24 Oct, 2019 1 commit
    • TensorCore Support using Intrinsic (#4136) · 324a9607
      * add tensor core support
      
      * avoid memory bank conflict
      
      * fix thread sync & better performance
      
      * better performance
      
      * add schedule test for conv2d
      
      * extend into BatchMatMul
      
      * support config fragment shape and layout using intrinsic
      
      * add TensorCore tutorial
      
      * add int support and fix lint
      
      * address comment
      
      * add 32*16*8 TensorCore test
      
      * fix wmma include logic
      Siyuan Feng committed
  19. 10 Oct, 2019 1 commit
  20. 08 Oct, 2019 1 commit
  21. 28 Sep, 2019 1 commit
  22. 13 Sep, 2019 1 commit
  23. 09 Sep, 2019 1 commit
  24. 07 Sep, 2019 1 commit
    • [VTA] Support TLPP in function simulator. (#3555) · 50c4546f
      * [VTA] Support TLPP in function simulator.
      Issue:
      currently vta function simulator just doing serialized instruction
      execution, the dependency logic of runtime ISA which use for task
      level pipe line parallelism can not get verified by function simulator.
      
      Solution:
      make the simulator driver to be multiple thread and support TLPP.
      
      Benefit:
      TLPP support VTA function simulator would make VTA logic testing/debug
      /change more easy.
      
      replace boost lockfree queue
      
      add configure control for simulator tlpp enable or disable.
      
      change code tyle into google style.
      
      Wrap queue read/write and sync logic to make function call more simple.
      
      Add some comments.
      
      Remove MT logic, change into Single thread mode.
      
      address review comments.
      
      code style change to match google code style and add comments.
      
      add cmake macro to enable/disable simulator tlpp logic.
      
      submodule update.
      
      correct file name mentioned in comments.
      
      * remove USE_VTA_FSIM_TLPP.
      Hua Jiang committed
  25. 05 Sep, 2019 3 commits
    • [VTA][TOPI] Conv2d transpose (deconvolution) operator support (#3777) · 23c22812
      * initial conv2d_transpose
      
      * correct select operator
      
      * cleanup
      
      * fix
      
      * fix correcness check
      
      * conv2d transpose declaration fix
      
      * autotvm conv2d_transpose tuning script
      
      * ir pass fix
      
      * fix tuning script
      
      * deriving params from env, adding bias
      
      * removing bias comp from deconvolution
      
      * lint
      
      * fix
      
      * lint
      
      * lint
      
      * turning off cpu
      
      * lint, ops
      
      * lint
      
      * import fix
      
      * removing hard coded values
      
      * lint
      Thierry Moreau committed
    • [VTA][Relay] Extending Vision model coverage compilation for VTA (#3740) · 028f47ce
      * adding support for graphpack over multiply op
      
      * increasing resnet model coverage
      
      * fix indentation
      
      * lint
      
      * moving recursion limit fix into graphpack pass
      
      * moving recursionlimit to relay init
      
      * pooling on NCHWnc format
      
      * adding more models
      
      * deploy_resnet_on_vta.py
      
      * trailing line
      
      * generalizing to vision models
      
      * merge conflicts
      
      * fix, apply quantization to VTA only
      
      * improving comments
      
      * trimming models that have runtime issues for the moment
      
      * lint
      
      * lint
      
      * lint
      Thierry Moreau committed
    • [VTA] de10-nano driver (#3394) · 734df8d5
      * rework;
      
      * `de10-nano` -> `de10nano`;
      
      * fix compilation error;
      
      * bug fix;
      
      * Update install.md
      
      * Update install.md
      
      * Update install.md
      
      * update with current runtime;
      
      * add debug messages;
      
      * bug fix in cma kernel module;
      Liangfu Chen committed
  26. 04 Sep, 2019 2 commits
  27. 03 Sep, 2019 1 commit
  28. 02 Sep, 2019 1 commit
  29. 01 Sep, 2019 1 commit
  30. 29 Aug, 2019 1 commit
    • [VTA] Fix RewriteForceSerial Function logic issue. (#3854) · 187600da
      Issue:
      RewriteForceSerial is a debug function to force instructions
      to be serialize instead of parrallel running, by doing so we
      can isolate some parallel problem or do performance compare
      between parallel and serialize. But this function have some
      problem, once get enabled by set debug flag, vta would stuck
      when running on pynq board.
      
      Analysis:
      once enable RewriteForceSerial, the dependency logic is different
      with default one, but we still use same logic to generate FINISH
      and other logic, this would cause dead lock.
      
      Solution:
      give a different dependency settings when enable RewriteForceSerial.
      Hua Jiang committed
  31. 27 Aug, 2019 1 commit
  32. 26 Aug, 2019 1 commit
    • [VTA][TSIM] Introduce Virtual Memory for TSIM Driver (#3686) · 92b6ca71
      * initial virtual memory;
      
      * initial integration;
      
      * include the header file in cmake;
      
      * implement allocation with virtual to logical address mapping;
      
      * virtual memory for tsim_driver;
      
      * implement the missing memory release function;
      
      * readability improvement;
      
      * readability improvement;
      
      * address review comments;
      
      * improved robustness in virtual memory allocation;
      
      * remove VTA_TSIM_USE_VIRTUAL_MEMORY macro and use virtual memory for tsim by default;
      
      * link tvm against vta library;
      
      * merge with master
      
      * build virtual memory system without linking tvm against vta;
      
      * minor change;
      
      * reuse VTA_PAGE_BYTES;
      
      * using DRAM class from sim_driver as VirtualMemoryManager;
      
      * satisfy linter;
      
      * add comments in code;
      
      * undo changes to Makefile
      
      * undo changes to Makefile
      
      * retrigger ci;
      
      * retrigger ci;
      
      * directly call into VirtualMemoryManager::Global()
      Liangfu Chen committed
  33. 18 Aug, 2019 1 commit