Add tests for commits:
- Add "wreduce -keepdc";
- Add "fmcombine -initeq -anyeq";
- Add "stat -tech xilinx";
- Add "synth_xilinx -arch".

Testing problems:

1.scc_feedback - Feedback is detected not in each case(with different
options).
2.splice/splice_port - No any changes in the dump after splice -port
command.
3.test_cell/test_cell_macc - ERROR: Assert `port_declared == true'
failed in kernel/rtlil.cc:1352.

This reverts commit c9a8d4a8.

Add new tests to backends and architecture;
Merge commit "Add regression test for Yosys PR 896"

Testing problems:

1. "sat -tempinduct_def":
+#ERROR: Assert `!undef_mode || model_undef' failed in
./kernel/satgen.h:90.

2. "share -force":
+#ERROR: Abort in passes/opt/share.cc:724.

Add tests for splitnets command
Expand coverage for trace command
Expand coverage for splice command (tests for options)
Expand coverage for scc command (different loops)
Expand coverage for rename command
Change test for passes/techmap/deminout
Update test for 'dff2dffe -direct' command
Add test for 'dffsr2dff' command
Expand coverage for iopadmap command

simple & misc
===========
Note that some of commands you can not test with checking with testbench
so those place in misc.

1. passes/cmds/add.cc
Note that here you need to load some existing verilog and add additional
wires, inputs or outputs
2. passes/cmds/blackbox.cc
you could create design with sub module, execute blackbox  and check if
sub module is replaced with blackbox module.
3. passes/cmds/bugpoint.cc

4. passes/cmds/chformal.cc

5. passes/cmds/chtype.cc

6. passes/cmds/connect.cc
Maybe can be covered together with add command

7.passes/cmds/connwrappers.cc

8. passes/cmds/design.cc
missing covering -import option

9.passes/cmds/plugin.cc

10. passes/cmds/rename.cc
rename parts of existing design

11. /passes/cmds/select.cc
Lot of options is not used , so room to improve

12.passes/cmds/setattr.cc
note there are 3 commands to cover here

13. passes/cmds/setundef.cc
setting with one, anyseq, anyconst ...

14. passes/sat/assertpmux.cc
15. passes/sat/async2sync.cc
16. passes/sat/eval.cc
17. passes/sat/freduce.cc
18. passes/sat/miter.cc
run with -assert option
19. passes/sat/sat.cc
many options are not tested
20. passes/sat/sim.cc

21. passes/techmap/flowmap.cc

backends
=======
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419

simple
=========
+ 1. passes/techmap/attrmap.cc
There is example in help block create example with
(* keep="true" *) attribute and run example

+ 2. passes/techmap/dff2dffe.cc
execute with  -unmap parameter

+ 3. passes/techmap/dff2dffs.cc

+ 4. passes/techmap/extract.cc
Lot of variations of input parameters is not excersised

? 5. passes/techmap/extract_counter.cc
This is specific to greenpak4 architecture, but idea is to have counter
in design and call this after synth_greenpak

+ 6. passes/techmap/shregmap.cc.
This also seams to be greenpak4 specific, but extracting shift register

misc
========
1. passes/techmap/insbuf.cc

Testing problems:
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419
2.dff2dffe -direct - skipped: ERROR: Found error in internal cell
\dffe.$procdff$47 ($dffe) at
3.insbuf -buf $_BUF_ in out - skipped: ERROR: Found error in internal
cell