Commit 94b2476e by SergeyDegtyar

Add tests for errors from 'abc' command.

parent 7f4fafc4
......@@ -175,9 +175,10 @@ $(eval $(call template,tee, tee))
$(eval $(call template,test_autotb, test_autotb test_autotb_file test_autotb_n test_autotb_seed))
#abc
$(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
$(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
$(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff))
$(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff))
$(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
$(eval $(call template,abc_error, abc_cannot_open abc_constr_no_liberty abc_lut_liberty abc_unsup_gate_type abc_inv_luts_synt abc_dff abc_return_code abc_clk_domain_not_found abc_script_o abc_script_top))
#hilomap
$(eval $(call template,hilomap, hilomap hilomap_hicell hilomap_locell hilomap_singleton hilomap_hicell_singleton hilomap_locell_singleton hilomap_hicell_locell_singleton))
......
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign cout = x / y * cin;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
read_verilog ../top.v
synth -top top
tee -o result.log abc -liberty -constr
abc -liberty -constr
read_verilog ../top.v
synth -top top
tee -o result.log abc -dff -clk u
abc -dff -clk u
read_verilog ../top.v
synth -top top
tee -o result.log abc -constr -liberty
abc -constr -liberty
read_verilog ../top.v
synth -top top
tee -o result.log abc -dff
abc -dff
read_verilog ../top.v
synth -top top
tee -o result.log abc -luts :
abc -liberty -luts :
read_verilog ../top.v
synth -top top
tee -o result.log abc -lut 2 -liberty top.lib
abc -lut 2 -liberty top.lib
read_verilog ../top.v
synth -top top
tee -o result.log abc -g XOR
abc -g XOR
read_verilog ../top.v
synth -top top
tee -o result.log abc -script o
abc -script o
read_verilog ../top.v
synth -top top
tee -o result.log abc -script top.ys
abc -script top.ys
read_verilog ../top.v
synth -top top
tee -o result.log abc -g XO
abc -g XO
read_verilog ../top.v
synth_xilinx
tee -o result.log stat -tech xilinx
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