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yosys-tests
Commit 971f4827 by SergeyDegtyar
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Add tests for error messages in 'misc' test group.

parent ba27324d
Showing with 1108 additions and 2 deletions
architecture/scripts/synth_xilinx_nosrt.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -nosrl
write_verilog synth.v
misc/add_error/top.v 0 → 100644
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/bugpoint_error/script.ys 0 → 100644
read_verilog ../top2.v
abc -g cmos4
misc/bugpoint_error/top.v 0 → 100644
module bb
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top
(
input x,
input y,
input cin,
output A,
output cout
);
bb u_bb (x,y,cin,A,cout);
endmodule
misc/bugpoint_error/top2.v 0 → 100644
module bb2
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top2
(
input x,
input y,
input cin,
output A,
output cout
);
bb2 u_bb2 (x,y,cin,A,cout);
endmodule
misc/check/top.v
module top
( input d, clk, output reg q );
wire u;
always @( posedge clk )
q <= d;
endmodule
misc/check/top1.v 0 → 100644
module top
( input d, clk, output reg q );
wire u;
wire s;
assign u = s;
assign u = d;
assign u = clk;
always @( posedge clk )
q <= u;
endmodule
misc/check_error/top.v 0 → 100644
module top
( input d, clk, output reg q );
wire u;
wire s;
assign u = s;
assign u = d;
assign u = clk;
always @( posedge clk )
q <= u;
endmodule
misc/chformal_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/chparam_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
parameter X = 1;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/connect_error/top.v 0 → 100644
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
misc/connect_error/top_2.v 0 → 100644
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top2
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
misc/cover_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/design_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/eval_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o),.y(1'b0));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire w;
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/eval_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
wire w;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o),.y(1'b0));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
// input y,
output o
);
assign o = x;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/eval_error/top_err_2.v 0 → 100644
module top
(
input [7:0] x,
input[7:0] y,
input cin,
output reg [7:0] A,
output [7:0] cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle #(7) u_mid (.x(x),.o(o),.y(1'b0));
middle #(0) u_mid2 (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
x,
y,
o
);
parameter u = 7;
input [u:0] x;
input [u:0] y;
output [u:0] o;
assign o = x + y;
endmodule
module xiddle
(
input [1:0] x,
input y,
output [1:0] o
);
assign o = x + y;
endmodule
misc/eval_error/top_err_3.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o),.y(1'b0));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire w;
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/fmcombine_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.o(o),.y(1'b0));
middle u_mid2 (.x(x),.o(o),.y(1'b1));
middle u_mid3 (.x(x),.o(o),.y(1'bX));
middle u_mid4 (.x(x),.o(o),.y(1'bX));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/fmcombine_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
parameter U = "string";
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.o(o),.y(1'b0));
middle u_mid2 (.x(x),.o(o),.y(1'b1));
middle u_mid3 (.x(x),.o(o),.y(1'bX));
middle u_mid4 (.x(x),.o(o),.y(1'bX));
urtl u_urtl (.x(x),.o(o),.y(y));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
parameter u = 12;
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/freduce_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/freduce_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(o),.o(x));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire ll;
assign ll = x & o;
assign o = y & ll;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/miter_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/miter_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
// input y,
output o
);
assign o = x;
endmodule
misc/mutate_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/plugin_error/top.v 0 → 100644
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
misc/rename_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire dd;
assign o = x + y;
endmodule
module low ();
endmodule
misc/sat_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
initial A = 0;
initial cout = 0;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/scc_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/scripts/add_error.ys 0 → 100644
read_verilog ../top.v
add -input i 2
add -wire i 2
tee -o result.log dump
misc/scripts/bugpoint_do_not_crash.ys 0 → 100644
read_verilog ../top.v
tee -o result.log bugpoint -script ../script.ys -connections
misc/scripts/bugpoint_fully_selected_des.ys 0 → 100644
read_verilog ../top.v
select bb
tee -o result.log bugpoint -script ../script.ys
misc/scripts/bugpoint_grep_string_not_found.ys 0 → 100644
read_verilog ../top.v
tee -o result.log bugpoint -script ../script.ys -grep "SSS"
misc/scripts/bugpoint_missing_script.ys 0 → 100644
read_verilog ../top.v
tee -o result.log bugpoint
misc/scripts/check_error.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log check -assert
misc/scripts/check_initdrv.ys
read_verilog -sv ../top.v
read_verilog -sv ../top1.v
proc
tee -o result.log check -initdrv
misc/scripts/check_noinit.ys
read_verilog -sv ../top.v
read_verilog -sv ../top1.v
proc
tee -o result.log check -noinit
misc/scripts/chformal_error.ys 0 → 100644
read_verilog -sv ../top.v
chformal
tee -o result.log dump
misc/scripts/chparam_error.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log chparam -set X 2 -list top
misc/scripts/connect_cannot_parse_set_lhs_expr.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set sdf sdf
misc/scripts/connect_cannot_parse_set_rhs_expr.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d sdf
misc/scripts/connect_cant_find_cell.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -port $procddff$2 D d
misc/scripts/connect_failed_parse_unset.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -unset sdf
misc/scripts/connect_failed_to_parse_port_expr.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -port $procdff$2 D dd
misc/scripts/connect_found_process.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log connect -unset d q
misc/scripts/connect_multiple_modules.ys 0 → 100644
read_verilog -sv ../top_2.v
proc
tee -o result.log connect -unset d q
misc/scripts/connect_no_modules.ys 0 → 100644
tee -o result.log connect -unset d q
misc/scripts/connect_opt_expected.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect
misc/scripts/connect_port_with_nounset.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -port $procdff$2 D d -nounset d
misc/scripts/connect_set_with_port.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d q -port $procdff$2 D d
misc/scripts/connect_set_with_unset.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d q -unset d
misc/scripts/connect_set_with_unset_and_port.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d q -unset d -port $procdff$2 D d
misc/scripts/connect_unset_with_nounset.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -unset d -nounset d
misc/scripts/connect_unset_with_nounset_and_port.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -unset d -port $procdff$2 D d -nounset d
misc/scripts/connect_unset_with_port.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -unset d -port $procdff$2 D d
misc/scripts/cover_cant_create_file.ys 0 → 100644
read_verilog ../top.v
tee -o result.log cover -o aa/out.txt
misc/scripts/design_no_pushed_design.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log design -pop
misc/scripts/design_no_saved_design_copy_from.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log design -copy-from first -as top_2 top
misc/scripts/design_no_saved_design_import.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log design -import first top
misc/scripts/design_no_saved_design_load.ys 0 → 100644
read_verilog -sv ../top.v
proc
design -load first
misc/scripts/design_no_top_module.ys 0 → 100644
read_verilog -sv ../top.v
design -save first
tee -o result.log design -import first
misc/scripts/eval_cant_find_input.ys 0 → 100644
read_verilog ../top_err_1.v
tee -o result.log eval -vloghammer_report mid dle s 1
misc/scripts/eval_cant_find_mod_1.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker u top
misc/scripts/eval_cant_find_mod_2.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker top u
misc/scripts/eval_cant_find_mod_in_curr_des.ys 0 → 100644
read_verilog ../top.v
tee -o result.log eval -vloghammer_report middle dle x 1
misc/scripts/eval_cant_find_mod_in_curr_dess.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -vloghammer_report mid dle x 1
misc/scripts/eval_diff_lhs_rhs_sizes.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -set x 1 -set y 2'b11 u_rtl
misc/scripts/eval_empty_selection.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval u
misc/scripts/eval_failed_to_parse_lhs.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -set u 0 middle
misc/scripts/eval_failed_to_parse_pattern.ys 0 → 100644
read_verilog ../top.v
tee -o result.log eval -vloghammer_report mid dle x d
misc/scripts/eval_failed_to_parse_rhs.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -set x u middle
misc/scripts/eval_failed_to_parse_show_expr.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -show u middle
misc/scripts/eval_failed_to_parse_table_expr.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -table u middle
misc/scripts/eval_has_no_counterpart.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker top u_rtl
misc/scripts/eval_mods_arent_equiv.ys 0 → 100644
read_verilog ../top_err_1.v
proc
tee -o result.log eval -brute_force_equiv_checker middle u_rtl
misc/scripts/eval_no_output_wire.ys 0 → 100644
read_verilog ../top_err_1.v
tee -o result.log eval -vloghammer_report mid dle x 1
misc/scripts/eval_only_one_module.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval
misc/scripts/eval_pattern_is_to_short.ys 0 → 100644
read_verilog ../top_err_2.v
tee -o result.log eval -vloghammer_report mid dle x 1'b1
misc/scripts/eval_port_doesnt_match.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker u_rtl top
misc/scripts/eval_rhs_expr.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -set x 1 -set y x u_rtl
misc/scripts/eval_two_distinct_solutions.ys 0 → 100644
read_verilog ../top_err_3.v
tee -o result.log eval -vloghammer_report u_ rtl x 1'b1
misc/scripts/eval_wire_isnt_an_input.ys 0 → 100644
read_verilog ../top.v
tee -o result.log eval -vloghammer_report mid dle w 1
misc/scripts/fmcombine_gate_cell_not_found.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log fmcombine top u_mid1 u_mid8
misc/scripts/fmcombine_gold_cell_not_found.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log fmcombine top u_mid8 u_mid3
misc/scripts/fmcombine_invalid_number_of_param.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log fmcombine
misc/scripts/fmcombine_module_not_found.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log fmcombine topp u_mid1 u_mid3
misc/scripts/fmcombine_nop_with_bwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -nop -bwd top u_mid1 u_mid2
misc/scripts/fmcombine_nop_with_fwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -nop -fwd top u_mid1 u_mid2
misc/scripts/fmcombine_nop_with_fwd_bwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -nop -fwd -bwd top u_mid1 u_mid2
misc/scripts/fmcombine_types_not_match.ys 0 → 100644
read_verilog ../top_err_1.v
proc
tee -o result.log fmcombine top u_mid1 u_urtl
misc/scripts/freduce_logic_loop.ys 0 → 100644
read_verilog ../top_err_1.v
tee -o result.log freduce
proc
tee -o result.log freduce
synth
tee -o result.log freduce
misc/scripts/miter_cant_find_gate_module.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter -equiv top gate top
misc/scripts/miter_cant_find_gold_module.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter -equiv gold gate top
misc/scripts/miter_cant_find_module.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter -assert t
misc/scripts/miter_missing_mode_param.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter
misc/scripts/miter_no_match_in_gate.ys 0 → 100644
read_verilog -sv ../top_err_1.v
proc
tee -o result.log miter -equiv middle u_rtl top1
misc/scripts/miter_no_match_in_gold.ys 0 → 100644
read_verilog -sv ../top_err_1.v
proc
tee -o result.log miter -equiv u_rtl middle top1
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