Some of the shift expanders accepted nonmemory_operands but were only
able to handle register_operands or CONST_INTs.  This is probably
academic without SVE, since we're not likely to see shifts by other
types of constant (const_wide_ints, consts, etc).  But for SVE,
it's possible for a vectorised shift induction to have a CONST_POLY_INT
shift amount.

This patch makes the expanders use aarch64_reg_or_imm instead.

2017-11-07  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3)
	(rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of
	nonmmory_operand.

From-SVN: r254499

2017-11-07  Richard Biener  <rguenther@suse.de>

	* match.pd: Fix build.

From-SVN: r254498

Canonicalize x / (- y) into (-x) / y.

This moves negates out of the RHS of a division in order to
allow further simplifications and potentially more reciprocal CSEs.

2017-11-07  Wilco Dijkstra  <wdijkstr@arm.com>
	    Jackson Woodruff  <jackson.woodruff@arm.com>

    gcc/
	PR tree-optimization/71026
	* match.pd: Canonicalize negate in division.

    testsuite/
	PR 71026/tree-optimization/71026
	* gcc.dg/div_neg: New test.

From-SVN: r254497

Currently the code A << (B - C) is not simplified.
However at least a more specific case of 1U << (C -x) where
C = precision(type) - 1 can be simplified to (1 << C) >> x.

This is done by adding a new simplification rule in match.pd.

2017-11-07  Sudakshina Das  <sudi.das@arm.com>

    gcc/
	PR middle-end/80131
	* match.pd: Simplify 1 << (C - x) where C = precision (x) - 1.

    testsuite/
	PR middle-end/80131
	* testsuite/gcc.dg/pr80131-1.c: New Test.

From-SVN: r254496

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

gcc/
	* match.pd ((a&~b)|(a^b),(a&~b)^~a,(a|b)&~(a^b),a|~(a^b),
	(a|b)|(a&^b),(a&b)|~(a^b),~(~a&b),~X^Y): New transformations.

gcc/testsuite/
	* gcc.dg/tree-ssa/bitops-1.c: New file.

From-SVN: r254495

gcc/ChangeLog:

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

	* fold-const.c (negate_expr_p) [PLUS_EXPR, MINUS_EXPR]: Handle
	non-scalar integral types.
	* match.pd (negate_expr_p): Handle MINUS_EXPR.
	(-(A-B), -(~A)): New transformations.

gcc/testsuite/ChangeLog:

2017-11-07  Marc Glisse  <marc.glisse@inria.fr>

	* gcc.dg/tree-ssa/negminus.c: New test.

From-SVN: r254494

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	* config/powerpcspe/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Remove
	semicolon after "do {} while (0)".
	* config/powerpcspe/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/powerpcspe/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/powerpcspe/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/powerpcspe/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/powerpcspe/aix71.h (SUBTARGET_OVERRIDE_OPTIONS): Same.

From-SVN: r254493

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	* config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Remove semicolon
	after "do {} while (0)".
	* config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Same.
	* config/rs6000/aix71.h (SUBTARGET_OVERRIDE_OPTIONS): Same.

From-SVN: r254492

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	* config/rs6000/aix-unwind.h (REGISTER_CFA_OFFSET_FOR): Remove semicolon
	after "do {} while (0)".

From-SVN: r254491

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	PR other/82784
	* config/arm/arm.c (HANDLE_NARROW_SHIFT_ARITH): Remove semicolon after
	"while {} do (0)".
	(arm_rtx_costs_internal): Add missing semicolon after
	HANDLE_NARROW_SHIFT_ARITH call.

From-SVN: r254490

2017-11-07  Tom de Vries  <tom@codesourcery.com>

	PR other/82784
	* config/aarch64/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Remove
	semicolon after "do {} while (0)".
	* config/i386/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
	* config/ia64/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
	* config/mips/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.
	* config/rs6000/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Same.

From-SVN: r254489

	* typeck2.c (build_m_component_ref): Also accept in lower stds with
	a pedwarn.

From-SVN: r254487

gcc currently uses ngettext in a number of places (gcc/cp/pt.c,
gcc/diagnostic.c, gcc/collect2.c).  Apparently there are (or used to
be) gettext implementations that lack ngettext.  See config/gettext.m4.

This patch arranges for intl/ to be compiled when the system gettext
lacks ngettext.

	* configure.ac: Invoke AM_GNU_GETTEXT with need_ngettext.
	* configure: Regenerate.

From-SVN: r254486

We want to actually use isel, so we shouldn't disable it.  It is
already not set by default on CPUs that don't have it, or where we
do not want to use it.


	* config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
	disable isel if it was not set explicitly.

From-SVN: r254485

FT32 makes use of multiple address spaces. When trying to inspect
objects in GDB, GDB was treating them as a straight "const". The cause
seems to be in GCC DWARF2 output.

This output is handled in gcc/gcc/dwarf2out.c, where modified_type_die()
checks that TYPE has qualifiers CV_QUALS. However while TYPE has
ADDR_SPACE qualifiers, the modified_type_die() explicitly discards the
ADDR_SPACE qualifiers.

This patch retains the ADDR_SPACE qualifiers as modified_type_die()
outputs the DWARF type tree.  This allows the types to match, and correct
type information for the object is emitted.

[gcc]

2017-11-06  James Bowman  <james.bowman@ftdichip.com>

	* gcc/dwarf2out.c (modified_type_die): Retain ADDR_SPACE
	qualifiers.
        (add_type_attribute) likewise.

From-SVN: r254484

From-SVN: r254483

When there is no need to make a copy of ix86_frame, we can use reference
of struct ix86_frame to avoid copy.

Tested on x86-64.

	* config/i386/i386.c (ix86_can_use_return_insn_p): Use reference
	of struct ix86_frame.
	(ix86_initial_elimination_offset): Likewise.
	(ix86_expand_split_stack_prologue): Likewise.

From-SVN: r254480

	* gcc.target/i386/stack-check-12.c: Revert to initial version.  Then..
	Add -fomit-frame-pointer.

From-SVN: r254479

2017-11-06  Marc Glisse  <marc.glisse@inria.fr>

	* tree-vrp.h (enum value_range_type): Update stale comment.

From-SVN: r254478

2017-11-06  François Dumont  <fdumont@gcc.gnu.org>

	* testsuite/libstdc++-prettyprinters/tr1.cc:  Compile with -O0.

From-SVN: r254477

    
    Currently the runtime is hard-coded to non-escape in various places.
    Don't run escape analysis for runtime.
    
    Reviewed-on: https://go-review.googlesource.com/76210

From-SVN: r254476

    
    "make check" runs make recursively to check each package. Pass
    the flags through. So it is possible to run "make check" with
    different settings easily.
    
    Reviewed-on: https://go-review.googlesource.com/76029

From-SVN: r254475

This patch passes the number of units to aarch64_expand_vec_perm
and aarch64_expand_vec_perm_const, which avoids a to_constant ()
once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_expand_vec_perm)
	(aarch64_expand_vec_perm_const): Take the number of units too.
	* config/aarch64/aarch64.c (aarch64_expand_vec_perm)
	(aarch64_expand_vec_perm_const): Likewise.
	* config/aarch64/aarch64-simd.md (vec_perm_const<mode>)
	(vec_perm<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254469

This patch passes the number of units to aarch64_simd_vect_par_cnst_half,
which avoids a to_constant () once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_simd_vect_par_cnst_half):
	Take the number of units too.
	* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Likewise.
	(aarch64_simd_check_vect_par_cnst_half): Update call accordingly,
	but check for a vector mode before rather than after the call.
	* config/aarch64/aarch64-simd.md (aarch64_split_simd_mov<mode>)
	(move_hi_quad_<mode>, vec_unpack<su>_hi_<mode>)
	(vec_unpack<su>_lo_<mode, vec_widen_<su>mult_lo_<mode>)
	(vec_widen_<su>mult_hi_<mode>, vec_unpacks_lo_<mode>)
	(vec_unpacks_hi_<mode>, aarch64_saddl2<mode>, aarch64_uaddl2<mode>)
	(aarch64_ssubl2<mode>, aarch64_usubl2<mode>, widen_ssum<mode>3)
	(widen_usum<mode>3, aarch64_saddw2<mode>, aarch64_uaddw2<mode>)
	(aarch64_ssubw2<mode>, aarch64_usubw2<mode>, aarch64_sqdmlal2<mode>)
	(aarch64_sqdmlsl2<mode>, aarch64_sqdmlal2_lane<mode>)
	(aarch64_sqdmlal2_laneq<mode>, aarch64_sqdmlsl2_lane<mode>)
	(aarch64_sqdmlsl2_laneq<mode>, aarch64_sqdmlal2_n<mode>)
	(aarch64_sqdmlsl2_n<mode>, aarch64_sqdmull2<mode>)
	(aarch64_sqdmull2_lane<mode>, aarch64_sqdmull2_laneq<mode>)
	(aarch64_sqdmull2_n<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254468

This patch passes the number of units to aarch64_reverse_mask,
which avoids a to_constant () once GET_MODE_NUNITS is variable.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_reverse_mask): Take
	the number of units too.
	* config/aarch64/aarch64.c (aarch64_reverse_mask): Likewise.
	* config/aarch64/aarch64-simd.md (vec_load_lanesoi<mode>)
	(vec_store_lanesoi<mode>, vec_load_lanesci<mode>)
	(vec_store_lanesci<mode>, vec_load_lanesxi<mode>)
	(vec_store_lanesxi<mode>): Update accordingly.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254467

Later patches turn the number of vector units into a poly_int.
We deliberately don't support applying GEN_INT to those (except
in target code that doesn't distinguish between poly_ints and normal
constants); gen_int_mode needs to be used instead.

This patch therefore replaces instances of:

  GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc])))

with uses of a new endian_lane_rtx function.

2017-11-06  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_endian_lane_rtx): Declare.
	* config/aarch64/aarch64.c (aarch64_endian_lane_rtx): New function.
	* config/aarch64/aarch64.h (ENDIAN_LANE_N): Take the number
	of units rather than the mode.
	* config/aarch64/iterators.md (nunits): New mode attribute.
	* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args):
	Use aarch64_endian_lane_rtx instead of GEN_INT (ENDIAN_LANE_N ...).
	* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>)
	(aarch64_dup_lane_<vswap_width_name><mode>, *aarch64_mul3_elt<mode>)
	(*aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
	(*aarch64_mul3_elt_to_64v2df, *aarch64_mla_elt<mode>): Likewise.
	(*aarch64_mla_elt_<vswap_width_name><mode>, *aarch64_mls_elt<mode>)
	(*aarch64_mls_elt_<vswap_width_name><mode>, *aarch64_fma4_elt<mode>)
	(*aarch64_fma4_elt_<vswap_width_name><mode>):: Likewise.
	(*aarch64_fma4_elt_to_64v2df, *aarch64_fnma4_elt<mode>): Likewise.
	(*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
	(*aarch64_fnma4_elt_to_64v2df, reduc_plus_scal_<mode>): Likewise.
	(reduc_plus_scal_v4sf, reduc_<maxmin_uns>_scal_<mode>): Likewise.
	(reduc_<maxmin_uns>_scal_<mode>): Likewise.
	(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
	(*aarch64_get_lane_zero_extendsi<mode>): Likewise.
	(aarch64_get_lane<mode>, *aarch64_mulx_elt_<vswap_width_name><mode>)
	(*aarch64_mulx_elt<mode>, *aarch64_vgetfmulx<mode>): Likewise.
	(aarch64_sq<r>dmulh_lane<mode>, aarch64_sq<r>dmulh_laneq<mode>)
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Likewise.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l_lane<mode>): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Likewise.
	(aarch64_sqdmull_lane<mode>, aarch64_sqdmull_laneq<mode>): Likewise.
	(aarch64_sqdmull2_lane<mode>_internal): Likewise.
	(aarch64_sqdmull2_laneq<mode>_internal): Likewise.
	(aarch64_vec_load_lanesoi_lane<mode>): Likewise.
	(aarch64_vec_store_lanesoi_lane<mode>): Likewise.
	(aarch64_vec_load_lanesci_lane<mode>): Likewise.
	(aarch64_vec_store_lanesci_lane<mode>): Likewise.
	(aarch64_vec_load_lanesxi_lane<mode>): Likewise.
	(aarch64_vec_store_lanesxi_lane<mode>): Likewise.
	(aarch64_simd_vec_set<mode>): Update use of ENDIAN_LANE_N.
	(aarch64_simd_vec_setv2di): Likewise.

Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254466

From-SVN: r254465

gcc/ChangeLog:

2017-11-06  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c.c (P8V_BUILTIN_VEC_REVB): Add power 8
	definitions.
	(P9V_BUILTIN_VEC_REVB): Remove the power 9 instance definitions.
	* config/rs6000/altivec.h (vec_revb): Change the #define from power 9
	to power 8.
	* config/rs6000/r6000-protos.h (swap_endian_selector_for_mode): Add new
	extern declaration.
	* config/rs6000/rs6000.c (swap_endian_selector_for_mode): Add function.
	* config/rs6000/rs6000-builtin.def (BU_P8V_VSX_1, BU_P8V_OVERLOAD_1):
	Add power 8 macro expansions.
	(BU_P9V_OVERLOAD_1): Remove power 9 overload expansion.
	* config/rs6000/vsx.md (revb_<mode>): Add define_expand to generate
	power 8 instructions.  (VSX_XXBR): Add iterator.

gcc/testsuite/ChangeLog:

2017-11-06  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-revb-runnable.c: New runnable test file.

From-SVN: r254464

A recent change to remove the movdi_vfp_cortexa8 meant that ldrd was used in
ITs block even when arm_restrict_it was enabled.  Rather than just fixing this
latent issue, change the default of predicable_short_it to "no" so that only
16-bit instructions need to be marked with it.  As a result there are far fewer
patterns that need the attribute, and omitting predicable_short_it is no longer
causing issues.

	* config/arm/arm.md (predicable_short_it): Change default to "no",
	improve documentation, remove uses that are identical to the default.
	(enabled_for_depr_it): Rename to enabled_for_short_it.
	* gcc/config/arm/arm-fixed.md (predicable_short_it): Remove default uses.
	* gcc/config/arm/ldmstm.md (predicable_short_it): Likewise.
	* gcc/config/arm/sync.md (predicable_short_it): Likewise.
	* gcc/config/arm/thumb2.md (predicable_short_it): Likewise.
	* gcc/config/arm/vfp.md (predicable_short_it): Likewise.

From-SVN: r254463

[gcc]
2017-11-06  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/82748
	* config/rs6000/rs6000-builtin.def (BU_FLOAT128_1): Delete
	float128 helper macros, which are no longer used after deleting
	the old 'q' built-in functions, and moving the round to odd
	built-in functions to being special built-in functions.
	(BU_FLOAT128_2): Likewise.
	(BU_FLOAT128_1_HW): Likewise.
	(BU_FLOAT128_2_HW): Likewise.
	(BU_FLOAT128_3_HW): Likewise.
	(FABSQ): Delete old 'q' built-in functions.
	(COPYSIGNQ): Likewise.
	(SQRTF128_ODD): Move round to odd built-in functions to be
	special built-in functions, so that we can handle
	-mabi=ieeelongdouble.
	(TRUNCF128_ODD): Likewise.
	(ADDF128_ODD): Likewise.
	(SUBF128_ODD): Likewise.
	(MULF128_ODD): Likewise.
	(DIVF128_ODD): Likewise.
	(FMAF128_ODD): Likewise.
	* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Map old 'q'
	built-in names to 'f128'.
	* config/rs6000/rs6000.c (rs6000_fold_builtin): Remove folding the
	old 'q' built-in functions, as the machine independent code for
	'f128' built-in functions handles this.
	(rs6000_expand_builtin): Add expansion for float128 round to odd
	functions, keying off on -mabi=ieeelongdouble of whether to use
	the KFmode or TFmode variant.
	(rs6000_init_builtins): Initialize the _Float128 round to odd
	built-in functions.
	* doc/extend.texi (PowerPC Built-in Functions): Document the old
	_Float128 'q' built-in functions are now mapped into the new
	'f128' built-in functions.

[gcc/testsuite]
2017-11-06  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/82748
	* gcc.target/powerpc/pr82748-1.c: New test.
	* gcc.target/powerpc/pr82748-2.c: Likewise.

From-SVN: r254462

re PR c++/65579 ([C++11] gcc requires definition of a static constexpr member even though it is not odr-used)

/cp
2017-11-06  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/65579
	* decl2.c (finish_static_data_member_decl): If there's an initializer,
	complete the type and re-apply the quals.

/testsuite
2017-11-06  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/65579
	* g++.dg/cpp0x/constexpr-template11.C: New.

From-SVN: r254461

* collect2.c (add_lto_object): Compile for OBJECT_COFF.
(scan_prog_file): Don't skip PASS_LTOINFO. Scan for LTO objects.

From-SVN: r254460

From-SVN: r254459

gcc/ChangeLog:
	PR jit/82826
	* ipa-fnsummary.c (ipa_fnsummary_c_finalize): New function.
	* ipa-fnsummary.h (ipa_fnsummary_c_finalize): New decl.
	* toplev.c: Include "ipa-fnsummary.h".
	(toplev::finalize): Call ipa_fnsummary_c_finalize.

From-SVN: r254458

	PR tree-optimization/82838
	* gimple-ssa-store-merging.c
	(imm_store_chain_info::output_merged_store): Call force_gimple_operand_1
	on a separate gimple_seq which is then appended to seq.

	* gcc.c-torture/compile/pr82838.c: New test.

From-SVN: r254457

re PR target/82788 (wrong code with -fstack-clash-protection --param=stack-clash-protection-probe-interval=10 on simple code)

	PR target/82788
	* config/i386/i386.c (PROBE_INTERVAL): Remove.
	(get_probe_interval): New functions.
	(ix86_adjust_stack_and_probe_stack_clash): Use get_probe_interval.
	(ix86_adjust_stack_and_probe): Likewise.
	(output_adjust_stack_and_probe): Likewise.
	(ix86_emit_probe_stack_range): Likewise.
	(ix86_expand_prologue): Likewise.

	PR target/82788
	* gcc.dg/pr82788.c: New test.

From-SVN: r254456

From-SVN: r254455

In this PR we tried to create a widening multiply of two 3-bit numbers,
but that isn't a widening multiply at the optab/rtl level, since both
the input and output still have the same mode.

We could trap this either in is_widening_mult_p or (as the patch does)
in the routines that actually ask for an optab.  The latter seemed
more natural since is_widening_mult_p doesn't otherwise care about modes.

2017-11-03  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	PR tree-optimization/82816
	* tree-ssa-math-opts.c (convert_mult_to_widen): Return false
	if the modes of the two types are the same.
	(convert_plusminus_to_widen): Likewise.

gcc/testsuite/
	* gcc.c-torture/compile/pr82816.c: New test.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254454

2017-11-06  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.md (*p9_vadu<mode>3) Rename to
	p9_vadu<mode>3.
	(usadv16qi): New define_expand.
	(usadv8hi): New define_expand.

[gcc/testsuite]

2017-11-06  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/sad-vectorize-1.c: New file.
	* gcc.target/powerpc/sad-vectorize-2.c: New file.
	* gcc.target/powerpc/sad-vectorize-3.c: New file.
	* gcc.target/powerpc/sad-vectorize-4.c: New file.

From-SVN: r254453

	PR bootstrap/82832
	* ipa-inline-transform.c (update_noncloned_frequencies): Always
	scale.
	(inline_transform): Likewise.
	* predict.c (counts_to_freqs): Remove useless conditional.
	* profile-count.h (profile_count::apply_scale): Move sanity check.
	* tree-inline.c (copy_bb): Always scale.
	(copy_cfg_body): Likewise.

From-SVN: r254452