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Commit fc504349 by Carl Love Committed by Carl Love
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rs6000-c.c (P8V_BUILTIN_VEC_REVB): Add power 8 definitions. 

gcc/ChangeLog:

2017-11-06  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c.c (P8V_BUILTIN_VEC_REVB): Add power 8
	definitions.
	(P9V_BUILTIN_VEC_REVB): Remove the power 9 instance definitions.
	* config/rs6000/altivec.h (vec_revb): Change the #define from power 9
	to power 8.
	* config/rs6000/r6000-protos.h (swap_endian_selector_for_mode): Add new
	extern declaration.
	* config/rs6000/rs6000.c (swap_endian_selector_for_mode): Add function.
	* config/rs6000/rs6000-builtin.def (BU_P8V_VSX_1, BU_P8V_OVERLOAD_1):
	Add power 8 macro expansions.
	(BU_P9V_OVERLOAD_1): Remove power 9 overload expansion.
	* config/rs6000/vsx.md (revb_<mode>): Add define_expand to generate
	power 8 instructions.  (VSX_XXBR): Add iterator.

gcc/testsuite/ChangeLog:

2017-11-06  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-revb-runnable.c: New runnable test file.

From-SVN: r254464
parent 113c53c3
Showing with 510 additions and 25 deletions
gcc/ChangeLog
2017-11-06 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c (P8V_BUILTIN_VEC_REVB): Add power 8
definitions.
(P9V_BUILTIN_VEC_REVB): Remove the power 9 instance definitions.
* config/rs6000/altivec.h (vec_revb): Change the #define from power 9
to power 8.
* config/rs6000/r6000-protos.h (swap_endian_selector_for_mode): Add new
extern declaration.
* config/rs6000/rs6000.c (swap_endian_selector_for_mode): Add function.
* config/rs6000/rs6000-builtin.def (BU_P8V_VSX_1, BU_P8V_OVERLOAD_1):
Add power 8 macro expansions.
(BU_P9V_OVERLOAD_1): Remove power 9 overload expansion.
* config/rs6000/vsx.md (revb_<mode>): Add define_expand to generate
power 8 instructions. (VSX_XXBR): Add iterator.
2017-11-06 Wilco Dijkstra <wdijkstr@arm.com> 2017-11-06 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (predicable_short_it): Change default to "no", * config/arm/arm.md (predicable_short_it): Change default to "no",
gcc/config/rs6000/altivec.h
...@@ -415,6 +415,7 @@ ...@@ -415,6 +415,7 @@
#define vec_vsubuqm __builtin_vec_vsubuqm #define vec_vsubuqm __builtin_vec_vsubuqm
#define vec_vupkhsw __builtin_vec_vupkhsw #define vec_vupkhsw __builtin_vec_vupkhsw
#define vec_vupklsw __builtin_vec_vupklsw #define vec_vupklsw __builtin_vec_vupklsw
#define vec_revb __builtin_vec_revb
#endif #endif
#ifdef __POWER9_VECTOR__ #ifdef __POWER9_VECTOR__
...@@ -478,8 +479,6 @@ ...@@ -478,8 +479,6 @@
#define vec_xlx __builtin_vec_vextulx #define vec_xlx __builtin_vec_vextulx
#define vec_xrx __builtin_vec_vexturx #define vec_xrx __builtin_vec_vexturx
#define vec_revb __builtin_vec_revb
#endif #endif
/* Predicates. /* Predicates.
......
gcc/config/rs6000/rs6000-builtin.def
...@@ -1850,6 +1850,13 @@ BU_P6_64BIT_2 (CMPB, "cmpb", CONST, cmpbdi3) ...@@ -1850,6 +1850,13 @@ BU_P6_64BIT_2 (CMPB, "cmpb", CONST, cmpbdi3)
/* 1 argument VSX instructions added in ISA 2.07. */ /* 1 argument VSX instructions added in ISA 2.07. */
BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn) BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn)
BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn) BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn)
BU_P8V_VSX_1 (REVB_V1TI, "revb_v1ti", CONST, revb_v1ti)
BU_P8V_VSX_1 (REVB_V2DI, "revb_v2di", CONST, revb_v2di)
BU_P8V_VSX_1 (REVB_V4SI, "revb_v4si", CONST, revb_v4si)
BU_P8V_VSX_1 (REVB_V8HI, "revb_v8hi", CONST, revb_v8hi)
BU_P8V_VSX_1 (REVB_V16QI, "revb_v16qi", CONST, revb_v16qi)
BU_P8V_VSX_1 (REVB_V2DF, "revb_v2df", CONST, revb_v2df)
BU_P8V_VSX_1 (REVB_V4SF, "revb_v4sf", CONST, revb_v4sf)
/* 1 argument altivec instructions added in ISA 2.07. */ /* 1 argument altivec instructions added in ISA 2.07. */
BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2) BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2)
...@@ -1959,6 +1966,7 @@ BU_P8V_OVERLOAD_1 (VPOPCNTUH, "vpopcntuh") ...@@ -1959,6 +1966,7 @@ BU_P8V_OVERLOAD_1 (VPOPCNTUH, "vpopcntuh")
BU_P8V_OVERLOAD_1 (VPOPCNTUW, "vpopcntuw") BU_P8V_OVERLOAD_1 (VPOPCNTUW, "vpopcntuw")
BU_P8V_OVERLOAD_1 (VPOPCNTUD, "vpopcntud") BU_P8V_OVERLOAD_1 (VPOPCNTUD, "vpopcntud")
BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd") BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd")
BU_P8V_OVERLOAD_1 (REVB, "revb")
/* ISA 2.07 vector overloaded 2 argument functions. */ /* ISA 2.07 vector overloaded 2 argument functions. */
BU_P8V_OVERLOAD_2 (EQV, "eqv") BU_P8V_OVERLOAD_2 (EQV, "eqv")
...@@ -2070,8 +2078,6 @@ BU_P9V_OVERLOAD_1 (VSTDCNQP, "scalar_test_neg_qp") ...@@ -2070,8 +2078,6 @@ BU_P9V_OVERLOAD_1 (VSTDCNQP, "scalar_test_neg_qp")
BU_P9V_OVERLOAD_1 (VSTDCNDP, "scalar_test_neg_dp") BU_P9V_OVERLOAD_1 (VSTDCNDP, "scalar_test_neg_dp")
BU_P9V_OVERLOAD_1 (VSTDCNSP, "scalar_test_neg_sp") BU_P9V_OVERLOAD_1 (VSTDCNSP, "scalar_test_neg_sp")
BU_P9V_OVERLOAD_1 (REVB, "revb")
BU_P9V_OVERLOAD_1 (VEXTRACT_FP_FROM_SHORTH, "vextract_fp_from_shorth") BU_P9V_OVERLOAD_1 (VEXTRACT_FP_FROM_SHORTH, "vextract_fp_from_shorth")
BU_P9V_OVERLOAD_1 (VEXTRACT_FP_FROM_SHORTL, "vextract_fp_from_shortl") BU_P9V_OVERLOAD_1 (VEXTRACT_FP_FROM_SHORTL, "vextract_fp_from_shortl")
......
gcc/config/rs6000/rs6000-c.c
...@@ -5562,36 +5562,38 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { ...@@ -5562,36 +5562,38 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, 0 }, RS6000_BTI_unsigned_V16QI, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
{ P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
{ P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DF, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 }, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SF, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 }, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI, { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
{ P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
{ P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
{ P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
......
gcc/config/rs6000/rs6000-protos.h
...@@ -136,6 +136,8 @@ extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx); ...@@ -136,6 +136,8 @@ extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);
extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx); extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
extern void rs6000_split_signbit (rtx, rtx); extern void rs6000_split_signbit (rtx, rtx);
extern void rs6000_expand_atomic_compare_and_swap (rtx op[]); extern void rs6000_expand_atomic_compare_and_swap (rtx op[]);
extern rtx swap_endian_selector_for_mode (machine_mode mode);
extern void rs6000_expand_atomic_exchange (rtx op[]); extern void rs6000_expand_atomic_exchange (rtx op[]);
extern void rs6000_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx); extern void rs6000_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
extern void rs6000_emit_swdiv (rtx, rtx, rtx, bool); extern void rs6000_emit_swdiv (rtx, rtx, rtx, bool);
......
gcc/config/rs6000/rs6000.c
...@@ -14303,6 +14303,77 @@ swap_selector_for_mode (machine_mode mode) ...@@ -14303,6 +14303,77 @@ swap_selector_for_mode (machine_mode mode)
return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm))); return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
} }
rtx
swap_endian_selector_for_mode (machine_mode mode)
{
unsigned int le_swap1[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
unsigned int le_swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
unsigned int le_swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
unsigned int le_swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
unsigned int le_swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
unsigned int be_swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
unsigned int be_swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
unsigned int be_swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
unsigned int be_swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
unsigned int be_swap16[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
unsigned int *swaparray, i;
rtx perm[16];
if (VECTOR_ELT_ORDER_BIG)
switch (mode)
{
case E_V1TImode:
swaparray = le_swap1;
break;
case E_V2DFmode:
case E_V2DImode:
swaparray = le_swap2;
break;
case E_V4SFmode:
case E_V4SImode:
swaparray = le_swap4;
break;
case E_V8HImode:
swaparray = le_swap8;
break;
case E_V16QImode:
swaparray = le_swap16;
break;
default:
gcc_unreachable ();
}
else
switch (mode)
{
case E_V1TImode:
swaparray = be_swap1;
break;
case E_V2DFmode:
case E_V2DImode:
swaparray = be_swap2;
break;
case E_V4SFmode:
case E_V4SImode:
swaparray = be_swap4;
break;
case E_V8HImode:
swaparray = be_swap8;
break;
case E_V16QImode:
swaparray = be_swap16;
break;
default:
gcc_unreachable ();
}
for (i = 0; i < 16; ++i)
perm[i] = GEN_INT (swaparray[i]);
return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
gen_rtvec_v (16, perm)));
}
/* Generate code for an "lvxl", or "lve*x" built-in for a little endian target /* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
with -maltivec=be specified. Issue the load followed by an element- with -maltivec=be specified. Issue the load followed by an element-
reversing permute. */ reversing permute. */
gcc/config/rs6000/vsx.md
...@@ -73,6 +73,13 @@ ...@@ -73,6 +73,13 @@
(TF "FLOAT128_VECTOR_P (TFmode)") (TF "FLOAT128_VECTOR_P (TFmode)")
TI]) TI])
(define_mode_attr VSX_XXBR [(V8HI "h")
(V4SI "w")
(V4SF "w")
(V2DF "d")
(V2DI "d")
(V1TI "q")])
;; Map into the appropriate load/store name based on the type ;; Map into the appropriate load/store name based on the type
(define_mode_attr VSm [(V16QI "vw4") (define_mode_attr VSm [(V16QI "vw4")
(V8HI "vw4") (V8HI "vw4")
...@@ -273,6 +280,9 @@ ...@@ -273,6 +280,9 @@
(define_mode_iterator VSINT_84 [V4SI V2DI DI SI]) (define_mode_iterator VSINT_84 [V4SI V2DI DI SI])
(define_mode_iterator VSINT_842 [V8HI V4SI V2DI]) (define_mode_iterator VSINT_842 [V8HI V4SI V2DI])
;; Vector reverse byte modes
(define_mode_iterator VEC_REVB [V8HI V4SI V2DI V4SF V2DF V1TI])
;; Iterator for ISA 3.0 vector extract/insert of small integer vectors. ;; Iterator for ISA 3.0 vector extract/insert of small integer vectors.
;; VSX_EXTRACT_I2 doesn't include V4SImode because SI extracts can be ;; VSX_EXTRACT_I2 doesn't include V4SImode because SI extracts can be
;; done on ISA 2.07 and not just ISA 3.0. ;; done on ISA 2.07 and not just ISA 3.0.
...@@ -4776,6 +4786,37 @@ ...@@ -4776,6 +4786,37 @@
"xxbrw %x0,%x1" "xxbrw %x0,%x1"
[(set_attr "type" "vecperm")]) [(set_attr "type" "vecperm")])
;; Swap all bytes in each element of vector
(define_expand "revb_<mode>"
[(set (match_operand:VEC_REVB 0 "vsx_register_operand")
(bswap:VEC_REVB (match_operand:VEC_REVB 1 "vsx_register_operand")))]
""
{
if (TARGET_P9_VECTOR)
emit_insn (gen_p9_xxbr<VSX_XXBR>_<mode> (operands[0], operands[1]));
else
{
/* Want to have the elements in reverse order relative
to the endian mode in use, i.e. in LE mode, put elements
in BE order. */
rtx sel = swap_endian_selector_for_mode(<MODE>mode);
emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1],
operands[1], sel));
}
DONE;
})
;; Reversing bytes in vector char is just a NOP.
(define_expand "revb_v16qi"
[(set (match_operand:V16QI 0 "vsx_register_operand")
(bswap:V16QI (match_operand:V16QI 1 "vsx_register_operand")))]
""
{
emit_move_insn (operands[0], operands[1]);
DONE;
})
;; Swap all bytes in each 16-bit element ;; Swap all bytes in each 16-bit element
(define_insn "p9_xxbrh_v8hi" (define_insn "p9_xxbrh_v8hi"
[(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")
......
gcc/testsuite/ChangeLog
2017-11-06 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-revb-runnable.c: New runnable test file.
2017-11-06 Michael Meissner <meissner@linux.vnet.ibm.com> 2017-11-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/82748 PR target/82748
......
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